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boundary="===============3496038778633622475==" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org --===============3496038778633622475== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="pxaf47l7hgrm57u2" Content-Disposition: inline --pxaf47l7hgrm57u2 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Mon, Dec 16, 2019 at 12:59:13AM +0800, Chen-Yu Tsai wrote: > From: Chen-Yu Tsai > > The CLK_POL field specifies whether data is sampled on the falling or > rising edge of PCLK, not whether the data lines are active high or low. > Evidence of this can be found in the timing diagram labeled "horizontal > size setting and pixel clock timing". > > Fix the setting by checking the correct flag, V4L2_MBUS_PCLK_SAMPLE_RISING. > While at it, reorder the three polarity flag checks so HSYNC and VSYNC > are grouped together. > > Fixes: 577bbf23b758 ("media: sunxi: Add A10 CSI driver") > Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard Thanks! Maxime --pxaf47l7hgrm57u2 Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCXfeIQwAKCRDj7w1vZxhR xVxhAP9flbDGwjgJDkotx80gPBlJVBaAWNlKf5+rVukqwTZs9AEA/EU/dnK5KzU0 QEqJQQjjDUSZ+fxuByQBiPtKJqftfQ0= =LpuS -----END PGP SIGNATURE----- --pxaf47l7hgrm57u2-- --===============3496038778633622475== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel --===============3496038778633622475==--