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From: Mathieu Poirier <mathieu.poirier@linaro.org>
To: gregkh@linuxfoundation.org
Cc: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 14/23] coresight: etmv4: Update default filter and initialisation
Date: Mon, 18 May 2020 12:02:33 -0600	[thread overview]
Message-ID: <20200518180242.7916-15-mathieu.poirier@linaro.org> (raw)
In-Reply-To: <20200518180242.7916-1-mathieu.poirier@linaro.org>

From: Mike Leach <mike.leach@linaro.org>

Differing default states set on driver init / perf init and as a result
of a sysfs reset.

The ETMv4 can be programmed to trace the entire instruction address range
without the need to use address comparator filter resources.
(Described in the ETMv4.x technical reference manual)

sysfs reset was using this method, perf and default driver init were setup
with an address range comparator for the entire address range.

The perf / driver init has been altered to use the method without needing
any comparator address hardware.

Minor adjustment to the vinst_ctrl register initialisation to ensure
correct zero initialisation.

Signed-off-by: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
 .../coresight/coresight-etm4x-sysfs.c         |  2 +-
 drivers/hwtracing/coresight/coresight-etm4x.c | 23 +++++--------------
 2 files changed, 7 insertions(+), 18 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
index ce41482431f9..b673e738bc9a 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
@@ -205,7 +205,7 @@ static ssize_t reset_store(struct device *dev,
 	 * started state. ARM recommends start-stop logic is set before
 	 * each trace run.
 	 */
-	config->vinst_ctrl |= BIT(0);
+	config->vinst_ctrl = BIT(0);
 	if (drvdata->nr_addr_cmp == true) {
 		config->mode |= ETM_MODE_VIEWINST_STARTSTOP;
 		/* SSSTATUS, bit[9] */
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
index 94c5f204998e..0b2c7c7efacb 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x.c
@@ -791,7 +791,7 @@ static void etm4_set_default_config(struct etmv4_config *config)
 	config->ts_ctrl = 0x0;
 
 	/* TRCVICTLR::EVENT = 0x01, select the always on logic */
-	config->vinst_ctrl |= BIT(0);
+	config->vinst_ctrl = BIT(0);
 }
 
 static u64 etm4_get_ns_access_type(struct etmv4_config *config)
@@ -894,17 +894,8 @@ static void etm4_set_start_stop_filter(struct etmv4_config *config,
 
 static void etm4_set_default_filter(struct etmv4_config *config)
 {
-	u64 start, stop;
-
-	/*
-	 * Configure address range comparator '0' to encompass all
-	 * possible addresses.
-	 */
-	start = 0x0;
-	stop = ~0x0;
-
-	etm4_set_comparator_filter(config, start, stop,
-				   ETM_DEFAULT_ADDR_COMP);
+	/* Trace everything 'default' filter achieved by no filtering */
+	config->viiectlr = 0x0;
 
 	/*
 	 * TRCVICTLR::SSSTATUS == 1, the start-stop logic is
@@ -925,11 +916,9 @@ static void etm4_set_default(struct etmv4_config *config)
 	/*
 	 * Make default initialisation trace everything
 	 *
-	 * Select the "always true" resource selector on the
-	 * "Enablign Event" line and configure address range comparator
-	 * '0' to trace all the possible address range.  From there
-	 * configure the "include/exclude" engine to include address
-	 * range comparator '0'.
+	 * This is done by a minimum default config sufficient to enable
+	 * full instruction trace - with a default filter for trace all
+	 * achieved by having no filtering.
 	 */
 	etm4_set_default_config(config);
 	etm4_set_default_filter(config);
-- 
2.20.1


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  parent reply	other threads:[~2020-05-18 18:07 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-18 18:02 [PATCH 00/23] coresight: next for v5.8 Mathieu Poirier
2020-05-18 18:02 ` [PATCH 01/23] coresight: Pass coresight_device for coresight_release_platform_data Mathieu Poirier
2020-05-18 18:02 ` [PATCH 02/23] coresight: Add return value for fixup connections Mathieu Poirier
2020-05-18 18:02 ` [PATCH 03/23] coresight: Add generic sysfs link creation functions Mathieu Poirier
2020-05-18 18:02 ` [PATCH 04/23] coresight: Expose device connections via sysfs Mathieu Poirier
2020-05-18 18:02 ` [PATCH 05/23] coresight: cti: Add in sysfs links to other coresight devices Mathieu Poirier
2020-05-18 18:02 ` [PATCH 06/23] coresight: docs: Add information about the topology representations Mathieu Poirier
2020-05-18 18:02 ` [PATCH 07/23] docs: trace: coresight-ect.rst: Fix a build warning Mathieu Poirier
2020-05-18 18:02 ` [PATCH 08/23] coresight: etm4x: Add support for Qualcomm SC7180 SoC Mathieu Poirier
2020-05-18 18:02 ` [PATCH 09/23] coresight: etm4x: Replace ETM PIDs with UCI IDs for Kryo385 Mathieu Poirier
2020-05-18 18:02 ` [PATCH 10/23] coresight: cti: Make some symbols static Mathieu Poirier
2020-05-18 18:02 ` [PATCH 11/23] coresight: etb10: Make coresight_etb_groups static Mathieu Poirier
2020-05-18 18:02 ` [PATCH 12/23] coresight: Fix support for sparsely populated ports Mathieu Poirier
2020-05-18 18:02 ` [PATCH 13/23] coresight: tmc: Fix TMC mode read in tmc_read_prepare_etb() Mathieu Poirier
2020-05-18 18:02 ` Mathieu Poirier [this message]
2020-05-18 18:02 ` [PATCH 15/23] coresight: etm4x: Add support for Neoverse N1 ETM Mathieu Poirier
2020-05-18 18:02 ` [PATCH 16/23] coresight: Mark some functions static Mathieu Poirier
2020-05-18 18:02 ` [PATCH 17/23] coresight: Don't initialize variables unnecessarily Mathieu Poirier
2020-05-18 18:02 ` [PATCH 18/23] coresight: Initialize arg in sparse friendly way Mathieu Poirier
2020-05-18 18:02 ` [PATCH 19/23] coresight: Include required headers in C files Mathieu Poirier
2020-05-18 18:02 ` [PATCH 20/23] coresight: Avoid casting void pointers Mathieu Poirier
2020-05-18 18:02 ` [PATCH 21/23] coresight: etm4x: Fix use-after-free of per-cpu etm drvdata Mathieu Poirier
2020-05-19 14:32   ` Greg KH
2020-05-18 18:02 ` [PATCH 22/23] coresight: cti: Add CPU Hotplug handling to CTI driver Mathieu Poirier
2020-05-18 18:02 ` [PATCH 23/23] coresight: cti: Add CPU idle pm notifer to CTI devices Mathieu Poirier

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