From: Thierry Reding <thierry.reding@gmail.com>
To: Thierry Reding <thierry.reding@gmail.com>,
Will Deacon <will@kernel.org>,
Robin Murphy <robin.murphy@arm.com>,
Joerg Roedel <joro@8bytes.org>,
Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Cc: iommu@lists.linux-foundation.org,
Jon Hunter <jonathanh@nvidia.com>,
Nicolin Chen <nicolinc@nvidia.com>,
linux-tegra@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 09/10] arm64: tegra: Enable SMMU support on Tegra194
Date: Tue, 20 Apr 2021 19:26:18 +0200 [thread overview]
Message-ID: <20210420172619.3782831-10-thierry.reding@gmail.com> (raw)
In-Reply-To: <20210420172619.3782831-1-thierry.reding@gmail.com>
From: Thierry Reding <treding@nvidia.com>
Add the device tree node for the dual-SMMU found on Tegra194 and hook up
peripherals such as host1x, BPMP, HDA, SDMMC, EQOS and VIC.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 86 ++++++++++++++++++++++++
1 file changed, 86 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index 4d37ee0ea4d1..6ed296e27158 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -62,6 +62,7 @@ ethernet@2490000 {
interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>,
<&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>;
interconnect-names = "dma-mem", "write";
+ iommus = <&smmu TEGRA194_SID_EQOS>;
status = "disabled";
snps,write-requests = <1>;
@@ -733,6 +734,7 @@ sdmmc1: mmc@3400000 {
interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>,
<&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>;
interconnect-names = "dma-mem", "write";
+ iommus = <&smmu TEGRA194_SID_SDMMC1>;
nvidia,pad-autocal-pull-up-offset-3v3-timeout =
<0x07>;
nvidia,pad-autocal-pull-down-offset-3v3-timeout =
@@ -759,6 +761,7 @@ sdmmc3: mmc@3440000 {
interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>,
<&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>;
interconnect-names = "dma-mem", "write";
+ iommus = <&smmu TEGRA194_SID_SDMMC3>;
nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
@@ -790,6 +793,7 @@ sdmmc4: mmc@3460000 {
interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>,
<&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>;
interconnect-names = "dma-mem", "write";
+ iommus = <&smmu TEGRA194_SID_SDMMC4>;
nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
@@ -821,6 +825,7 @@ hda@3510000 {
interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>,
<&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>;
interconnect-names = "dma-mem", "write";
+ iommus = <&smmu TEGRA194_SID_HDA>;
status = "disabled";
};
@@ -1300,6 +1305,84 @@ pmc: pmc@c360000 {
interrupt-controller;
};
+ smmu: iommu@12000000 {
+ compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500";
+ reg = <0x12000000 0x800000>,
+ <0x11000000 0x800000>;
+ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+ stream-match-mask = <0x7f80>;
+ #global-interrupts = <2>;
+ #iommu-cells = <1>;
+
+ nvidia,memory-controller = <&mc>;
+ status = "okay";
+ };
+
host1x@13e00000 {
compatible = "nvidia,tegra194-host1x";
reg = <0x13e00000 0x10000>,
@@ -1319,6 +1402,7 @@ host1x@13e00000 {
ranges = <0x15000000 0x15000000 0x01000000>;
interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>;
interconnect-names = "dma-mem";
+ iommus = <&smmu TEGRA194_SID_HOST1X>;
display-hub@15200000 {
compatible = "nvidia,tegra194-display";
@@ -1430,6 +1514,7 @@ vic@15340000 {
interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>,
<&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>;
interconnect-names = "dma-mem", "write";
+ iommus = <&smmu TEGRA194_SID_VIC>;
};
dpaux0: dpaux@155c0000 {
@@ -2136,6 +2221,7 @@ bpmp: bpmp {
<&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>,
<&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>;
interconnect-names = "read", "write", "dma-mem", "dma-write";
+ iommus = <&smmu TEGRA194_SID_BPMP>;
bpmp_i2c: i2c {
compatible = "nvidia,tegra186-bpmp-i2c";
--
2.30.2
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next prev parent reply other threads:[~2021-04-20 17:29 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-20 17:26 [PATCH v2 00/10] arm64: tegra: Prevent early SMMU faults Thierry Reding
2021-04-20 17:26 ` [PATCH v2 01/10] memory: tegra: Implement SID override programming Thierry Reding
2021-04-26 8:28 ` Krzysztof Kozlowski
2021-04-26 12:13 ` Thierry Reding
2021-04-26 14:10 ` Krzysztof Kozlowski
2021-04-20 17:26 ` [PATCH v2 02/10] dt-bindings: arm-smmu: Add Tegra186 compatible string Thierry Reding
2021-04-20 17:26 ` [PATCH v2 03/10] iommu/arm-smmu: Implement ->probe_finalize() Thierry Reding
2021-04-20 17:26 ` [PATCH v2 04/10] iommu/arm-smmu: tegra: Detect number of instances at runtime Thierry Reding
2021-04-20 22:06 ` Krishna Reddy
2021-04-20 17:26 ` [PATCH v2 05/10] iommu/arm-smmu: tegra: Implement SID override programming Thierry Reding
2021-04-20 17:26 ` [PATCH v2 06/10] iommu/arm-smmu: Use Tegra implementation on Tegra186 Thierry Reding
2021-04-20 17:26 ` [PATCH v2 07/10] arm64: tegra: Use correct compatible string for Tegra186 SMMU Thierry Reding
2021-04-20 17:26 ` [PATCH v2 08/10] arm64: tegra: Hook up memory controller to SMMU on Tegra186 Thierry Reding
2021-04-20 17:26 ` Thierry Reding [this message]
2021-04-20 17:26 ` [PATCH v2 10/10] arm64: tegra: Enable SMMU support for display on Tegra194 Thierry Reding
2021-05-28 17:05 ` [PATCH v2 00/10] arm64: tegra: Prevent early SMMU faults Thierry Reding
2021-06-01 12:26 ` Will Deacon
2021-06-01 18:08 ` Thierry Reding
2021-06-02 7:33 ` Krzysztof Kozlowski
2021-06-02 7:35 ` Krzysztof Kozlowski
2021-06-02 8:52 ` Thierry Reding
2021-06-02 10:44 ` Krzysztof Kozlowski
2021-06-02 11:40 ` Will Deacon
2021-06-02 14:58 ` Thierry Reding
2021-06-02 14:58 ` Krzysztof Kozlowski
2021-06-02 14:53 ` Thierry Reding
2021-06-02 14:57 ` Krzysztof Kozlowski
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