From: Mark Rutland <mark.rutland@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: catalin.marinas@arm.com, james.morse@arm.com,
mark.rutland@arm.com, maz@kernel.org, will@kernel.org,
joey.gouly@arm.com
Subject: [PATCH v2 07/19] arm64: entry: convert IRQ+FIQ handlers to C
Date: Wed, 19 May 2021 13:38:50 +0100 [thread overview]
Message-ID: <20210519123902.2452-8-mark.rutland@arm.com> (raw)
In-Reply-To: <20210519123902.2452-1-mark.rutland@arm.com>
For various reasons we'd like to convert the bulk of arm64's exception
triage logic to C. As a step towards that, this patch converts the EL1
and EL0 IRQ+FIQ triage logic to C.
Separate C functions are added for the native and compat cases so that
in subsequent patches we can handle native/compat differences in C.
Since the triage functions can now call arm64_apply_bp_hardening()
directly, the do_el0_irq_bp_hardening() wrapper function is removed.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: James Morse <james.morse@arm.com>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Will Deacon <will@kernel.org>
---
arch/arm64/include/asm/exception.h | 8 ++-
arch/arm64/include/asm/processor.h | 2 -
arch/arm64/kernel/entry-common.c | 86 +++++++++++++++++++++++++++++++--
arch/arm64/kernel/entry.S | 99 ++++++--------------------------------
arch/arm64/mm/fault.c | 7 ---
5 files changed, 102 insertions(+), 100 deletions(-)
diff --git a/arch/arm64/include/asm/exception.h b/arch/arm64/include/asm/exception.h
index c24b69c0c589..4284ee57a9a5 100644
--- a/arch/arm64/include/asm/exception.h
+++ b/arch/arm64/include/asm/exception.h
@@ -32,14 +32,18 @@ static inline u32 disr_to_esr(u64 disr)
}
asmlinkage void el1_sync_handler(struct pt_regs *regs);
+asmlinkage void el1_irq_handler(struct pt_regs *regs);
+asmlinkage void el1_fiq_handler(struct pt_regs *regs);
asmlinkage void el1_error_handler(struct pt_regs *regs);
asmlinkage void el0_sync_handler(struct pt_regs *regs);
+asmlinkage void el0_irq_handler(struct pt_regs *regs);
+asmlinkage void el0_fiq_handler(struct pt_regs *regs);
asmlinkage void el0_error_handler(struct pt_regs *regs);
asmlinkage void el0_sync_compat_handler(struct pt_regs *regs);
+asmlinkage void el0_irq_compat_handler(struct pt_regs *regs);
+asmlinkage void el0_fiq_compat_handler(struct pt_regs *regs);
asmlinkage void el0_error_compat_handler(struct pt_regs *regs);
-asmlinkage void noinstr enter_el1_irq_or_nmi(struct pt_regs *regs);
-asmlinkage void noinstr exit_el1_irq_or_nmi(struct pt_regs *regs);
asmlinkage void call_on_irq_stack(struct pt_regs *regs,
void (*func)(struct pt_regs *));
asmlinkage void enter_from_user_mode(void);
diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h
index 9df3feeee890..2f21c76324bb 100644
--- a/arch/arm64/include/asm/processor.h
+++ b/arch/arm64/include/asm/processor.h
@@ -257,8 +257,6 @@ void set_task_sctlr_el1(u64 sctlr);
extern struct task_struct *cpu_switch_to(struct task_struct *prev,
struct task_struct *next);
-asmlinkage void arm64_preempt_schedule_irq(void);
-
#define task_pt_regs(p) \
((struct pt_regs *)(THREAD_SIZE + task_stack_page(p)) - 1)
diff --git a/arch/arm64/kernel/entry-common.c b/arch/arm64/kernel/entry-common.c
index dbe0bb09fe86..9c0ed05b98c4 100644
--- a/arch/arm64/kernel/entry-common.c
+++ b/arch/arm64/kernel/entry-common.c
@@ -19,6 +19,8 @@
#include <asm/exception.h>
#include <asm/kprobes.h>
#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/stacktrace.h>
#include <asm/sysreg.h>
/*
@@ -101,7 +103,7 @@ void noinstr arm64_exit_nmi(struct pt_regs *regs)
__nmi_exit();
}
-asmlinkage void noinstr enter_el1_irq_or_nmi(struct pt_regs *regs)
+static void noinstr enter_el1_irq_or_nmi(struct pt_regs *regs)
{
if (IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI) && !interrupts_enabled(regs))
arm64_enter_nmi(regs);
@@ -109,7 +111,7 @@ asmlinkage void noinstr enter_el1_irq_or_nmi(struct pt_regs *regs)
enter_from_kernel_mode(regs);
}
-asmlinkage void noinstr exit_el1_irq_or_nmi(struct pt_regs *regs)
+static void noinstr exit_el1_irq_or_nmi(struct pt_regs *regs)
{
if (IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI) && !interrupts_enabled(regs))
arm64_exit_nmi(regs);
@@ -117,11 +119,11 @@ asmlinkage void noinstr exit_el1_irq_or_nmi(struct pt_regs *regs)
exit_to_kernel_mode(regs);
}
-asmlinkage void __sched arm64_preempt_schedule_irq(void)
+static void __sched arm64_preempt_schedule_irq(void)
{
lockdep_assert_irqs_disabled();
- if (preempt_count() != 0)
+ if (!IS_ENABLED(CONFIG_PREEMPTION) || preempt_count() != 0)
return;
/*
@@ -145,6 +147,18 @@ asmlinkage void __sched arm64_preempt_schedule_irq(void)
preempt_schedule_irq();
}
+static void do_interrupt_handler(struct pt_regs *regs,
+ void (*handler)(struct pt_regs *))
+{
+ if (on_thread_stack())
+ call_on_irq_stack(regs, handler);
+ else
+ handler(regs);
+}
+
+extern void (*handle_arch_irq)(struct pt_regs *);
+extern void (*handle_arch_fiq)(struct pt_regs *);
+
#ifdef CONFIG_ARM64_ERRATUM_1463225
static DEFINE_PER_CPU(int, __in_cortex_a76_erratum_1463225_wa);
@@ -311,6 +325,27 @@ asmlinkage void noinstr el1_sync_handler(struct pt_regs *regs)
}
}
+static void noinstr el1_interrupt(struct pt_regs *regs,
+ void (*handler)(struct pt_regs *))
+{
+ write_sysreg(DAIF_PROCCTX_NOIRQ, daif);
+
+ enter_el1_irq_or_nmi(regs);
+ do_interrupt_handler(regs, handler);
+ arm64_preempt_schedule_irq();
+ exit_el1_irq_or_nmi(regs);
+}
+
+asmlinkage void noinstr el1_irq_handler(struct pt_regs *regs)
+{
+ el1_interrupt(regs, handle_arch_irq);
+}
+
+asmlinkage void noinstr el1_fiq_handler(struct pt_regs *regs)
+{
+ el1_interrupt(regs, handle_arch_fiq);
+}
+
asmlinkage void noinstr el1_error_handler(struct pt_regs *regs)
{
unsigned long esr = read_sysreg(esr_el1);
@@ -510,6 +545,39 @@ asmlinkage void noinstr el0_sync_handler(struct pt_regs *regs)
}
}
+static void noinstr el0_interrupt(struct pt_regs *regs,
+ void (*handler)(struct pt_regs *))
+{
+ enter_from_user_mode();
+
+ write_sysreg(DAIF_PROCCTX_NOIRQ, daif);
+
+ if (regs->pc & BIT(55))
+ arm64_apply_bp_hardening();
+
+ do_interrupt_handler(regs, handler);
+}
+
+static void noinstr __el0_irq_handler_common(struct pt_regs *regs)
+{
+ el0_interrupt(regs, handle_arch_irq);
+}
+
+asmlinkage void noinstr el0_irq_handler(struct pt_regs *regs)
+{
+ __el0_irq_handler_common(regs);
+}
+
+static void noinstr __el0_fiq_handler_common(struct pt_regs *regs)
+{
+ el0_interrupt(regs, handle_arch_fiq);
+}
+
+asmlinkage void noinstr el0_fiq_handler(struct pt_regs *regs)
+{
+ __el0_fiq_handler_common(regs);
+}
+
static void __el0_error_handler_common(struct pt_regs *regs)
{
unsigned long esr = read_sysreg(esr_el1);
@@ -586,6 +654,16 @@ asmlinkage void noinstr el0_sync_compat_handler(struct pt_regs *regs)
}
}
+asmlinkage void noinstr el0_irq_compat_handler(struct pt_regs *regs)
+{
+ __el0_irq_handler_common(regs);
+}
+
+asmlinkage void noinstr el0_fiq_compat_handler(struct pt_regs *regs)
+{
+ __el0_fiq_handler_common(regs);
+}
+
asmlinkage void noinstr el0_error_compat_handler(struct pt_regs *regs)
{
__el0_error_handler_common(regs);
diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S
index 327a559679f7..eebc6e72125c 100644
--- a/arch/arm64/kernel/entry.S
+++ b/arch/arm64/kernel/entry.S
@@ -486,63 +486,12 @@ SYM_CODE_START_LOCAL(__swpan_exit_el0)
SYM_CODE_END(__swpan_exit_el0)
#endif
- .macro irq_stack_entry
- mov x19, sp // preserve the original sp
-#ifdef CONFIG_SHADOW_CALL_STACK
- mov x24, scs_sp // preserve the original shadow stack
-#endif
-
- /*
- * Compare sp with the base of the task stack.
- * If the top ~(THREAD_SIZE - 1) bits match, we are on a task stack,
- * and should switch to the irq stack.
- */
- ldr x25, [tsk, TSK_STACK]
- eor x25, x25, x19
- and x25, x25, #~(THREAD_SIZE - 1)
- cbnz x25, 9998f
-
- ldr_this_cpu x25, irq_stack_ptr, x26
- mov x26, #IRQ_STACK_SIZE
- add x26, x25, x26
-
- /* switch to the irq stack */
- mov sp, x26
-
-#ifdef CONFIG_SHADOW_CALL_STACK
- /* also switch to the irq shadow stack */
- ldr_this_cpu scs_sp, irq_shadow_call_stack_ptr, x26
-#endif
-
-9998:
- .endm
-
- /*
- * The callee-saved regs (x19-x29) should be preserved between
- * irq_stack_entry and irq_stack_exit, but note that kernel_entry
- * uses x20-x23 to store data for later use.
- */
- .macro irq_stack_exit
- mov sp, x19
-#ifdef CONFIG_SHADOW_CALL_STACK
- mov scs_sp, x24
-#endif
- .endm
-
/* GPRs used by entry code */
tsk .req x28 // current thread_info
/*
* Interrupt handling.
*/
- .macro irq_handler, handler:req
- ldr_l x1, \handler
- mov x0, sp
- irq_stack_entry
- blr x1
- irq_stack_exit
- .endm
-
.macro gic_prio_kentry_setup, tmp:req
#ifdef CONFIG_ARM64_PSEUDO_NMI
alternative_if ARM64_HAS_IRQ_PRIO_MASKING
@@ -552,32 +501,6 @@ tsk .req x28 // current thread_info
#endif
.endm
- .macro el1_interrupt_handler, handler:req
- enable_da
-
- mov x0, sp
- bl enter_el1_irq_or_nmi
-
- irq_handler \handler
-
-#ifdef CONFIG_PREEMPTION
- bl arm64_preempt_schedule_irq // irq en/disable is done inside
-#endif
-
- mov x0, sp
- bl exit_el1_irq_or_nmi
- .endm
-
- .macro el0_interrupt_handler, handler:req
- user_exit_irqoff
- enable_da
-
- tbz x22, #55, 1f
- bl do_el0_irq_bp_hardening
-1:
- irq_handler \handler
- .endm
-
.text
/*
@@ -701,13 +624,15 @@ SYM_CODE_END(el1_sync)
.align 6
SYM_CODE_START_LOCAL_NOALIGN(el1_irq)
kernel_entry 1
- el1_interrupt_handler handle_arch_irq
+ mov x0, sp
+ bl el1_irq_handler
kernel_exit 1
SYM_CODE_END(el1_irq)
SYM_CODE_START_LOCAL_NOALIGN(el1_fiq)
kernel_entry 1
- el1_interrupt_handler handle_arch_fiq
+ mov x0, sp
+ bl el1_fiq_handler
kernel_exit 1
SYM_CODE_END(el1_fiq)
@@ -734,12 +659,16 @@ SYM_CODE_END(el0_sync_compat)
.align 6
SYM_CODE_START_LOCAL_NOALIGN(el0_irq_compat)
kernel_entry 0, 32
- b el0_irq_naked
+ mov x0, sp
+ bl el0_irq_compat_handler
+ b ret_to_user
SYM_CODE_END(el0_irq_compat)
SYM_CODE_START_LOCAL_NOALIGN(el0_fiq_compat)
kernel_entry 0, 32
- b el0_fiq_naked
+ mov x0, sp
+ bl el0_fiq_compat_handler
+ b ret_to_user
SYM_CODE_END(el0_fiq_compat)
SYM_CODE_START_LOCAL_NOALIGN(el0_error_compat)
@@ -753,15 +682,15 @@ SYM_CODE_END(el0_error_compat)
.align 6
SYM_CODE_START_LOCAL_NOALIGN(el0_irq)
kernel_entry 0
-el0_irq_naked:
- el0_interrupt_handler handle_arch_irq
+ mov x0, sp
+ bl el0_irq_handler
b ret_to_user
SYM_CODE_END(el0_irq)
SYM_CODE_START_LOCAL_NOALIGN(el0_fiq)
kernel_entry 0
-el0_fiq_naked:
- el0_interrupt_handler handle_arch_fiq
+ mov x0, sp
+ bl el0_fiq_handler
b ret_to_user
SYM_CODE_END(el0_fiq)
diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c
index 871c82ab0a30..3b4a4adfddfd 100644
--- a/arch/arm64/mm/fault.c
+++ b/arch/arm64/mm/fault.c
@@ -836,13 +836,6 @@ void do_mem_abort(unsigned long far, unsigned int esr, struct pt_regs *regs)
}
NOKPROBE_SYMBOL(do_mem_abort);
-void do_el0_irq_bp_hardening(void)
-{
- /* PC has already been checked in entry.S */
- arm64_apply_bp_hardening();
-}
-NOKPROBE_SYMBOL(do_el0_irq_bp_hardening);
-
void do_sp_pc_abort(unsigned long addr, unsigned int esr, struct pt_regs *regs)
{
arm64_notify_die("SP/PC alignment exception", regs, SIGBUS, BUS_ADRALN,
--
2.11.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-05-19 13:09 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-19 12:38 [PATCH v2 00/19] arm64: entry: migrate more code to C Mark Rutland
2021-05-19 12:38 ` [PATCH v2 01/19] arm64: remove redundant local_daif_mask() in bad_mode() Mark Rutland
2021-05-21 10:39 ` Joey Gouly
2021-05-19 12:38 ` [PATCH v2 02/19] arm64: entry: unmask IRQ+FIQ after EL0 handling Mark Rutland
2021-05-25 16:45 ` Joey Gouly
2021-05-19 12:38 ` [PATCH v2 03/19] arm64: entry: convert SError handlers to C Mark Rutland
2021-05-25 13:38 ` Joey Gouly
2021-05-19 12:38 ` [PATCH v2 04/19] arm64: entry: move arm64_preempt_schedule_irq to entry-common.c Mark Rutland
2021-05-21 11:00 ` Joey Gouly
2021-05-19 12:38 ` [PATCH v2 05/19] arm64: entry: move preempt logic to C Mark Rutland
2021-05-25 12:50 ` Joey Gouly
2021-05-19 12:38 ` [PATCH v2 06/19] arm64: entry: add a call_on_irq_stack helper Mark Rutland
2021-05-19 14:46 ` Mark Rutland
2021-05-19 12:38 ` Mark Rutland [this message]
2021-05-21 13:19 ` [PATCH v2 07/19] arm64: entry: convert IRQ+FIQ handlers to C Joey Gouly
2021-05-21 15:23 ` Mark Rutland
2021-05-19 12:38 ` [PATCH v2 08/19] arm64: entry: organise entry handlers consistently Mark Rutland
2021-05-21 16:04 ` Joey Gouly
2021-05-19 12:38 ` [PATCH v2 09/19] arm64: entry: organise entry vectors consistently Mark Rutland
2021-05-21 16:07 ` Joey Gouly
2021-05-19 12:38 ` [PATCH v2 10/19] arm64: entry: consolidate EL1 exception returns Mark Rutland
2021-05-21 16:22 ` Joey Gouly
2021-05-19 12:38 ` [PATCH v2 11/19] arm64: entry: move bad_mode() to entry-common.c Mark Rutland
2021-05-21 16:46 ` Joey Gouly
2021-05-19 12:38 ` [PATCH v2 12/19] arm64: entry: improve bad_mode() Mark Rutland
2021-05-21 17:02 ` Joey Gouly
2021-05-21 17:10 ` Mark Rutland
2021-05-19 12:38 ` [PATCH v2 13/19] arm64: entry: template the entry asm functions Mark Rutland
2021-05-21 17:16 ` Joey Gouly
2021-05-19 12:38 ` [PATCH v2 14/19] arm64: entry: handle all vectors with C Mark Rutland
2021-05-21 15:59 ` Joey Gouly
2021-05-21 16:41 ` Mark Rutland
2021-05-19 12:38 ` [PATCH v2 15/19] arm64: entry: split bad stack entry Mark Rutland
2021-05-25 11:25 ` Joey Gouly
2021-05-19 12:38 ` [PATCH v2 16/19] arm64: entry: split SDEI entry Mark Rutland
2021-05-25 11:49 ` Joey Gouly
2021-05-19 12:39 ` [PATCH v2 17/19] arm64: entry: make NMI entry/exit functions static Mark Rutland
2021-05-21 17:21 ` Joey Gouly
2021-05-19 12:39 ` [PATCH v2 18/19] arm64: entry: don't instrument entry code with KCOV Mark Rutland
2021-05-19 12:39 ` [PATCH v2 19/19] arm64: idle: don't instrument idle " Mark Rutland
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210519123902.2452-8-mark.rutland@arm.com \
--to=mark.rutland@arm.com \
--cc=catalin.marinas@arm.com \
--cc=james.morse@arm.com \
--cc=joey.gouly@arm.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=maz@kernel.org \
--cc=will@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).