From: Bharat Bhushan <bbhushan2@marvell.com>
To: <will@kernel.org>, <mark.rutland@arm.com>, <robh+dt@kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<sgoutham@marvell.com>
Cc: Bharat Bhushan <bbhushan2@marvell.com>
Subject: [PATCH 4/4] perf/marvell: cn10k DDR perf event core ownership
Date: Mon, 26 Jul 2021 14:40:27 +0530 [thread overview]
Message-ID: <20210726091027.798-5-bbhushan2@marvell.com> (raw)
In-Reply-To: <20210726091027.798-1-bbhushan2@marvell.com>
As DDR perf event counters are not per core, so they
should be accessed only by one core at a time.
Select new core when previously owning core is going
offline.
Signed-off-by: Bharat Bhushan <bbhushan2@marvell.com>
---
drivers/perf/marvell_cn10k_ddr_pmu.c | 50 ++++++++++++++++++++++++++--
include/linux/cpuhotplug.h | 1 +
2 files changed, 49 insertions(+), 2 deletions(-)
diff --git a/drivers/perf/marvell_cn10k_ddr_pmu.c b/drivers/perf/marvell_cn10k_ddr_pmu.c
index 5e88fb7ffcb8..0b20c20c7f2f 100644
--- a/drivers/perf/marvell_cn10k_ddr_pmu.c
+++ b/drivers/perf/marvell_cn10k_ddr_pmu.c
@@ -130,6 +130,7 @@ struct cn10k_ddr_pmu {
int active_events;
struct perf_event *events[DDRC_PERF_NUM_COUNTERS];
struct hrtimer hrtimer;
+ struct hlist_node node;
};
#define to_cn10k_ddr_pmu(p) container_of(p, struct cn10k_ddr_pmu, pmu)
@@ -616,6 +617,24 @@ static enum hrtimer_restart cn10k_ddr_pmu_timer_handler(struct hrtimer *hrtimer)
return HRTIMER_RESTART;
}
+static int cn10k_ddr_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node)
+{
+ struct cn10k_ddr_pmu *pmu = hlist_entry_safe(node, struct cn10k_ddr_pmu,
+ node);
+ unsigned int target;
+
+ if (cpu != pmu->cpu)
+ return 0;
+
+ target = cpumask_any_but(cpu_online_mask, cpu);
+ if (target >= nr_cpu_ids)
+ return 0;
+
+ perf_pmu_migrate_context(&pmu->pmu, cpu, target);
+ pmu->cpu = target;
+ return 0;
+}
+
static int cn10k_ddr_perf_probe(struct platform_device *pdev)
{
struct cn10k_ddr_pmu *ddr_pmu;
@@ -669,20 +688,33 @@ static int cn10k_ddr_perf_probe(struct platform_device *pdev)
hrtimer_init(&ddr_pmu->hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
ddr_pmu->hrtimer.function = cn10k_ddr_pmu_timer_handler;
+ cpuhp_state_add_instance_nocalls(
+ CPUHP_AP_PERF_ARM_MARVELL_CN10K_DDR_ONLINE,
+ &ddr_pmu->node);
+
ret = perf_pmu_register(&ddr_pmu->pmu, name, -1);
if (ret)
- return ret;
+ goto error;
ddr_pmu->id = index++;
pr_info("CN10K DDR PMU Driver for ddrc@%llx - id-%d\n",
res->start, ddr_pmu->id);
return 0;
+error:
+ cpuhp_state_remove_instance_nocalls(
+ CPUHP_AP_PERF_ARM_MARVELL_CN10K_DDR_ONLINE,
+ &ddr_pmu->node);
+ return ret;
}
static int cn10k_ddr_perf_remove(struct platform_device *pdev)
{
struct cn10k_ddr_pmu *ddr_pmu = platform_get_drvdata(pdev);
+ cpuhp_state_remove_instance_nocalls(
+ CPUHP_AP_PERF_ARM_MARVELL_CN10K_DDR_ONLINE,
+ &ddr_pmu->node);
+
perf_pmu_unregister(&ddr_pmu->pmu);
return 0;
}
@@ -705,12 +737,26 @@ static struct platform_driver cn10k_ddr_pmu_driver = {
static int __init cn10k_ddr_pmu_init(void)
{
- return platform_driver_register(&cn10k_ddr_pmu_driver);
+ int ret;
+
+ ret = cpuhp_setup_state_multi(
+ CPUHP_AP_PERF_ARM_MARVELL_CN10K_DDR_ONLINE,
+ "perf/marvell/cn10k/ddr:online", NULL,
+ cn10k_ddr_pmu_offline_cpu);
+ if (ret)
+ return ret;
+
+ ret = platform_driver_register(&cn10k_ddr_pmu_driver);
+ if (ret)
+ cpuhp_remove_multi_state(
+ CPUHP_AP_PERF_ARM_MARVELL_CN10K_DDR_ONLINE);
+ return ret;
}
static void __exit cn10k_ddr_pmu_exit(void)
{
platform_driver_unregister(&cn10k_ddr_pmu_driver);
+ cpuhp_remove_multi_state(CPUHP_AP_PERF_ARM_MARVELL_CN10K_DDR_ONLINE);
}
module_init(cn10k_ddr_pmu_init);
diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h
index 47e13582d9fc..ce7f2740d7db 100644
--- a/include/linux/cpuhotplug.h
+++ b/include/linux/cpuhotplug.h
@@ -185,6 +185,7 @@ enum cpuhp_state {
CPUHP_AP_PERF_ARM_QCOM_L3_ONLINE,
CPUHP_AP_PERF_ARM_APM_XGENE_ONLINE,
CPUHP_AP_PERF_ARM_CAVIUM_TX2_UNCORE_ONLINE,
+ CPUHP_AP_PERF_ARM_MARVELL_CN10K_DDR_ONLINE,
CPUHP_AP_PERF_POWERPC_NEST_IMC_ONLINE,
CPUHP_AP_PERF_POWERPC_CORE_IMC_ONLINE,
CPUHP_AP_PERF_POWERPC_THREAD_IMC_ONLINE,
--
2.17.1
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prev parent reply other threads:[~2021-07-26 9:13 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-26 9:10 [PATCH 0/4] cn10k DDR Performance monitor support Bharat Bhushan
2021-07-26 9:10 ` [PATCH 1/4] dt-bindings: perf: marvell: cn10k ddr performance monitor Bharat Bhushan
2021-07-29 23:29 ` Rob Herring
2021-08-03 11:38 ` [EXT] " Bharat Bhushan
2021-07-26 9:10 ` [PATCH 2/4] perf/marvell: ADD cn10k DDR PMU basic support Bharat Bhushan
2021-07-26 9:10 ` [PATCH 3/4] perf/marvell: cn10k DDR perfmon event overflow handling Bharat Bhushan
2021-07-26 9:10 ` Bharat Bhushan [this message]
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