From: Nancy.Lin <nancy.lin@mediatek.com>
To: CK Hu <ck.hu@mediatek.com>
Cc: Chun-Kuang Hu <chunkuang.hu@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
Rob Herring <robh+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
"jason-jh . lin" <jason-jh.lin@mediatek.com>,
"Nancy . Lin" <nancy.lin@mediatek.com>,
Yongqiang Niu <yongqiang.niu@mediatek.com>,
<dri-devel@lists.freedesktop.org>,
<linux-mediatek@lists.infradead.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<singo.chang@mediatek.com>, <srv_heupstream@mediatek.com>
Subject: [PATCH v4 13/17] drm/mediatek: add display merge api support for MT8195
Date: Wed, 25 Aug 2021 18:05:27 +0800 [thread overview]
Message-ID: <20210825100531.5653-14-nancy.lin@mediatek.com> (raw)
In-Reply-To: <20210825100531.5653-1-nancy.lin@mediatek.com>
Add merge new API.
1. Vdosys1 merge1~merge4 support HW mute function, so add unmute API.
2. Add merge new advance config API. The original merge API is
mtk_ddp_comp_funcs function prototype. The API interface parameters
cannot be modified, so add a new config API for extension.
3. Add merge enable/disable API for cmdq support. The ovl_adaptor merges
are configured with each drm plane update. Need to enable/disable
merge with cmdq making sure all the settings taken effect in the
same vblank.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 6 ++
drivers/gpu/drm/mediatek/mtk_disp_merge.c | 74 ++++++++++++++++++++---
2 files changed, 70 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index b3a372cab0bd..2446ad0a4977 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -63,6 +63,12 @@ void mtk_merge_config(struct device *dev, unsigned int width,
unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
void mtk_merge_start(struct device *dev);
void mtk_merge_stop(struct device *dev);
+void mtk_merge_advance_config(struct device *dev, unsigned int l_w, unsigned int r_w,
+ unsigned int h, unsigned int vrefresh, unsigned int bpc,
+ struct cmdq_pkt *cmdq_pkt);
+void mtk_merge_unmute(struct device *dev, struct cmdq_pkt *cmdq_pkt);
+void mtk_merge_enable(struct device *dev, struct cmdq_pkt *cmdq_pkt);
+void mtk_merge_disable(struct device *dev, struct cmdq_pkt *cmdq_pkt);
void mtk_ovl_bgclr_in_on(struct device *dev);
void mtk_ovl_bgclr_in_off(struct device *dev);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
index b05e1df79c3d..41bff6d3a8da 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_merge.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
@@ -17,6 +17,7 @@
#define DISP_REG_MERGE_CTRL 0x000
#define MERGE_EN 1
#define DISP_REG_MERGE_CFG_0 0x010
+#define DISP_REG_MERGE_CFG_1 0x014
#define DISP_REG_MERGE_CFG_4 0x020
#define DISP_REG_MERGE_CFG_10 0x038
/* no swap */
@@ -25,9 +26,12 @@
#define DISP_REG_MERGE_CFG_12 0x040
#define CFG_10_10_1PI_2PO_BUF_MODE 6
#define CFG_10_10_2PI_2PO_BUF_MODE 8
+#define CFG_11_10_1PI_2PO_MERGE 18
#define FLD_CFG_MERGE_MODE GENMASK(4, 0)
#define DISP_REG_MERGE_CFG_24 0x070
#define DISP_REG_MERGE_CFG_25 0x074
+#define DISP_REG_MERGE_CFG_26 0x078
+#define DISP_REG_MERGE_CFG_27 0x07c
#define DISP_REG_MERGE_CFG_36 0x0a0
#define ULTRA_EN BIT(0)
#define PREULTRA_EN BIT(4)
@@ -54,26 +58,52 @@
#define FLD_PREULTRA_TH_LOW GENMASK(15, 0)
#define FLD_PREULTRA_TH_HIGH GENMASK(31, 16)
+#define DISP_REG_MERGE_MUTE_0 0xf00
+
struct mtk_disp_merge {
void __iomem *regs;
struct clk *clk;
struct clk *async_clk;
struct cmdq_client_reg cmdq_reg;
bool fifo_en;
+ bool mute_support;
};
void mtk_merge_start(struct device *dev)
+{
+ mtk_merge_enable(dev, NULL);
+}
+
+void mtk_merge_stop(struct device *dev)
{
struct mtk_disp_merge *priv = dev_get_drvdata(dev);
- writel(MERGE_EN, priv->regs + DISP_REG_MERGE_CTRL);
+ mtk_merge_disable(dev, NULL);
}
-void mtk_merge_stop(struct device *dev)
+void mtk_merge_enable(struct device *dev, struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+ mtk_ddp_write(cmdq_pkt, 1, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_CTRL);
+}
+
+void mtk_merge_disable(struct device *dev, struct cmdq_pkt *cmdq_pkt)
{
struct mtk_disp_merge *priv = dev_get_drvdata(dev);
- writel(0x0, priv->regs + DISP_REG_MERGE_CTRL);
+ mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_CTRL);
+}
+
+void mtk_merge_unmute(struct device *dev, struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+ if (priv->mute_support)
+ mtk_ddp_write(cmdq_pkt, 0x0, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_MUTE_0);
}
static void mtk_merge_fifo_setting(struct mtk_disp_merge *priv,
@@ -98,12 +128,19 @@ static void mtk_merge_fifo_setting(struct mtk_disp_merge *priv,
void mtk_merge_config(struct device *dev, unsigned int w,
unsigned int h, unsigned int vrefresh,
unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+ mtk_merge_advance_config(dev, w, 0, h, vrefresh, bpc, cmdq_pkt);
+}
+
+void mtk_merge_advance_config(struct device *dev, unsigned int l_w, unsigned int r_w,
+ unsigned int h, unsigned int vrefresh, unsigned int bpc,
+ struct cmdq_pkt *cmdq_pkt)
{
struct mtk_disp_merge *priv = dev_get_drvdata(dev);
unsigned int mode = CFG_10_10_1PI_2PO_BUF_MODE;
- if (!h || !w) {
- dev_err(dev, "%s: input width(%d) or height(%d) is invalid\n", __func__, w, h);
+ if (!h || !l_w) {
+ dev_err(dev, "%s: input width(%d) or height(%d) is invalid\n", __func__, l_w, h);
return;
}
@@ -112,14 +149,29 @@ void mtk_merge_config(struct device *dev, unsigned int w,
mode = CFG_10_10_2PI_2PO_BUF_MODE;
}
- mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+ if (r_w)
+ mode = CFG_11_10_1PI_2PO_MERGE;
+
+ mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs,
DISP_REG_MERGE_CFG_0);
- mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+ mtk_ddp_write(cmdq_pkt, h << 16 | r_w, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_CFG_1);
+ mtk_ddp_write(cmdq_pkt, h << 16 | (l_w + r_w), &priv->cmdq_reg, priv->regs,
DISP_REG_MERGE_CFG_4);
- mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+ mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs,
DISP_REG_MERGE_CFG_24);
- mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
- DISP_REG_MERGE_CFG_25);
+ if (r_w)
+ mtk_ddp_write(cmdq_pkt, h << 16 | r_w, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_CFG_25);
+ else
+ mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_CFG_25);
+
+ mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_CFG_26);
+ mtk_ddp_write(cmdq_pkt, h << 16 | r_w, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_CFG_27);
+
mtk_ddp_write_mask(cmdq_pkt, SWAP_MODE, &priv->cmdq_reg, priv->regs,
DISP_REG_MERGE_CFG_10, FLD_SWAP_MODE);
mtk_ddp_write_mask(cmdq_pkt, mode, &priv->cmdq_reg, priv->regs,
@@ -205,6 +257,8 @@ static int mtk_disp_merge_probe(struct platform_device *pdev)
priv->fifo_en = of_property_read_bool(dev->of_node,
"mediatek,merge-fifo-en");
+ priv->mute_support = of_property_read_bool(dev->of_node,
+ "mediatek,merge-mute");
platform_set_drvdata(pdev, priv);
ret = component_add(dev, &mtk_disp_merge_component_ops);
--
2.18.0
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next prev parent reply other threads:[~2021-08-25 10:16 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-25 10:05 [PATCH v4 00/17] Add MediaTek SoC DRM (vdosys1) support for mt8195 Nancy.Lin
2021-08-25 10:05 ` [PATCH v4 01/17] dt-bindings: mediatek: add vdosys1 RDMA definition " Nancy.Lin
2021-08-25 10:05 ` [PATCH v4 02/17] dt-bindings: mediatek: add vdosys1 MERGE property " Nancy.Lin
2021-08-25 10:05 ` [PATCH v4 03/17] dt-bindings: mediatek: add ethdr definition " Nancy.Lin
2021-08-25 10:05 ` [PATCH v4 04/17] dt-bindings: mediatek: Add #reset-cells to mmsys system controller Nancy.Lin
2021-08-25 10:05 ` [PATCH v4 05/17] dt-bindings: reset: mt8195: add vdosys1 reset control bit Nancy.Lin
2021-08-25 10:05 ` [PATCH v4 06/17] arm64: dts: mt8195: add display node for vdosys1 Nancy.Lin
2021-08-25 10:05 ` [PATCH v4 07/17] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1 Nancy.Lin
2021-08-25 10:05 ` [PATCH v4 08/17] soc: mediatek: add mtk-mmsys config API " Nancy.Lin
2021-08-25 10:05 ` [PATCH v4 09/17] soc: mediatek: add cmdq support of " Nancy.Lin
2021-08-25 10:05 ` [PATCH v4 10/17] soc: mediatek: mmsys: Add reset controller support for MT8195 vdosys1 Nancy.Lin
2021-08-25 10:46 ` Philipp Zabel
2021-09-06 2:07 ` Nancy.Lin
2021-08-25 10:05 ` [PATCH v4 11/17] soc: mediatek: add mtk-mutex support for mt8195 vdosys1 Nancy.Lin
2021-08-25 10:05 ` [PATCH v4 12/17] drm/mediatek: add display MDP RDMA support for MT8195 Nancy.Lin
2021-08-25 10:05 ` Nancy.Lin [this message]
2021-08-25 10:05 ` [PATCH v4 14/17] drm/mediatek: add ETHDR " Nancy.Lin
2021-08-25 10:05 ` [PATCH v4 15/17] drm/mediatek: add ovl_adaptor " Nancy.Lin
2021-08-25 10:05 ` [PATCH v4 16/17] drm/mediatek: modify mediatek-drm for mt8195 multi mmsys support Nancy.Lin
2021-08-25 10:05 ` [PATCH v4 17/17] drm/mediatek: add mediatek-drm of vdosys1 support for MT8195 Nancy.Lin
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