From: James Clark <james.clark@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
broonie@kernel.org, acme@kernel.org, leo.yan@linaro.org,
john.garry@huawei.com, catalin.marinas@arm.com, will@kernel.org,
James Clark <james.clark@arm.com>,
Jonathan Corbet <corbet@lwn.net>,
Mark Rutland <mark.rutland@arm.com>,
linux-doc@vger.kernel.org
Subject: [PATCH v3 2/2] arm64/sve: Add Perf extensions documentation
Date: Thu, 1 Sep 2022 14:26:58 +0100 [thread overview]
Message-ID: <20220901132658.1024635-3-james.clark@arm.com> (raw)
In-Reply-To: <20220901132658.1024635-1-james.clark@arm.com>
Document that the VG register is available in Perf samples
Signed-off-by: James Clark <james.clark@arm.com>
---
Documentation/arm64/sve.rst | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/Documentation/arm64/sve.rst b/Documentation/arm64/sve.rst
index 93c2c2990584..8955bf1bf757 100644
--- a/Documentation/arm64/sve.rst
+++ b/Documentation/arm64/sve.rst
@@ -452,6 +452,24 @@ The regset data starts with struct user_sve_header, containing:
* Modifying the system default vector length does not affect the vector length
of any existing process or thread that does not make an execve() call.
+10. Perf extensions
+--------------------------------
+
+* The arm64 specific DWARF standard [5] added the VG (Vector Granule) register
+ at index 46. This register is used for DWARF unwinding when variable length
+ SVE registers are pushed onto the stack.
+
+* Its value is equivalent to the current SVE vector length (VL) in bits divided
+ by 64.
+
+* The value is included in Perf samples in the regs[46] field if
+ PERF_SAMPLE_REGS_USER is set and the sample_regs_user mask has bit 46 set.
+
+* The value is the current value at the time the sample was taken, and it can
+ change over time.
+
+* If the system doesn't support SVE when perf_event_open is called with these
+ settings, the event will fail to open.
Appendix A. SVE programmer's model (informative)
=================================================
@@ -593,3 +611,5 @@ References
http://infocenter.arm.com/help/topic/com.arm.doc.ihi0055c/IHI0055C_beta_aapcs64.pdf
http://infocenter.arm.com/help/topic/com.arm.doc.subset.swdev.abi/index.html
Procedure Call Standard for the ARM 64-bit Architecture (AArch64)
+
+[5] https://github.com/ARM-software/abi-aa/blob/main/aadwarf64/aadwarf64.rst
--
2.28.0
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next prev parent reply other threads:[~2022-09-01 13:36 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-01 13:26 [PATCH v3 0/2] perf: arm64: Kernel support for Dwarf unwinding through SVE functions James Clark
2022-09-01 13:26 ` [PATCH v3 1/2] perf: arm64: Add SVE vector granule register to user regs James Clark
2022-09-01 13:26 ` James Clark [this message]
2022-09-01 13:33 ` [PATCH v3 2/2] arm64/sve: Add Perf extensions documentation Mark Brown
2022-09-20 10:28 ` James Clark
2022-09-22 14:04 ` [PATCH v3 0/2] perf: arm64: Kernel support for Dwarf unwinding through SVE functions Will Deacon
2022-09-22 14:31 ` James Clark
2022-09-22 20:57 ` Will Deacon
2022-09-22 20:33 ` Will Deacon
2022-09-23 9:32 ` James Clark
2022-09-23 12:36 ` Will Deacon
2022-09-23 12:43 ` James Clark
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