From: Chunfeng Yun <chunfeng.yun@mediatek.com>
To: Chun-Kuang Hu <chunkuang.hu@kernel.org>, Vinod Koul <vkoul@kernel.org>
Cc: Philipp Zabel <p.zabel@pengutronix.de>,
Chunfeng Yun <chunfeng.yun@mediatek.com>,
Kishon Vijay Abraham I <kishon@ti.com>,
"Matthias Brugger" <matthias.bgg@gmail.com>,
<dri-devel@lists.freedesktop.org>,
<linux-mediatek@lists.infradead.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-phy@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
Jitao Shi <jitao.shi@mediatek.com>,
Stanley Chu <stanley.chu@mediatek.com>
Subject: [PATCH 09/18] phy: mediatek: hdmi: mt8173: use GENMASK to generate bits mask
Date: Tue, 20 Sep 2022 17:00:29 +0800 [thread overview]
Message-ID: <20220920090038.15133-10-chunfeng.yun@mediatek.com> (raw)
In-Reply-To: <20220920090038.15133-1-chunfeng.yun@mediatek.com>
Use GENMASK() macro to generate bits mask
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c | 88 +++++++++++-----------
1 file changed, 44 insertions(+), 44 deletions(-)
diff --git a/drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c b/drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c
index 6cdfdf5a698a..55fe97f5465d 100644
--- a/drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c
+++ b/drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c
@@ -8,38 +8,38 @@
#define HDMI_CON0 0x00
#define RG_HDMITX_PLL_EN BIT(31)
-#define RG_HDMITX_PLL_FBKDIV (0x7f << 24)
+#define RG_HDMITX_PLL_FBKDIV GENMASK(30, 24)
#define PLL_FBKDIV_SHIFT 24
-#define RG_HDMITX_PLL_FBKSEL (0x3 << 22)
+#define RG_HDMITX_PLL_FBKSEL GENMASK(23, 22)
#define PLL_FBKSEL_SHIFT 22
-#define RG_HDMITX_PLL_PREDIV (0x3 << 20)
+#define RG_HDMITX_PLL_PREDIV GENMASK(21, 20)
#define PREDIV_SHIFT 20
-#define RG_HDMITX_PLL_POSDIV (0x3 << 18)
+#define RG_HDMITX_PLL_POSDIV GENMASK(19, 18)
#define POSDIV_SHIFT 18
-#define RG_HDMITX_PLL_RST_DLY (0x3 << 16)
-#define RG_HDMITX_PLL_IR (0xf << 12)
+#define RG_HDMITX_PLL_RST_DLY GENMASK(17, 16)
+#define RG_HDMITX_PLL_IR GENMASK(15, 12)
#define PLL_IR_SHIFT 12
-#define RG_HDMITX_PLL_IC (0xf << 8)
+#define RG_HDMITX_PLL_IC GENMASK(11, 8)
#define PLL_IC_SHIFT 8
-#define RG_HDMITX_PLL_BP (0xf << 4)
+#define RG_HDMITX_PLL_BP GENMASK(7, 4)
#define PLL_BP_SHIFT 4
-#define RG_HDMITX_PLL_BR (0x3 << 2)
+#define RG_HDMITX_PLL_BR GENMASK(3, 2)
#define PLL_BR_SHIFT 2
-#define RG_HDMITX_PLL_BC (0x3 << 0)
+#define RG_HDMITX_PLL_BC GENMASK(1, 0)
#define PLL_BC_SHIFT 0
#define HDMI_CON1 0x04
-#define RG_HDMITX_PLL_DIVEN (0x7 << 29)
+#define RG_HDMITX_PLL_DIVEN GENMASK(31, 29)
#define PLL_DIVEN_SHIFT 29
#define RG_HDMITX_PLL_AUTOK_EN BIT(28)
-#define RG_HDMITX_PLL_AUTOK_KF (0x3 << 26)
-#define RG_HDMITX_PLL_AUTOK_KS (0x3 << 24)
+#define RG_HDMITX_PLL_AUTOK_KF GENMASK(27, 26)
+#define RG_HDMITX_PLL_AUTOK_KS GENMASK(25, 24)
#define RG_HDMITX_PLL_AUTOK_LOAD BIT(23)
-#define RG_HDMITX_PLL_BAND (0x3f << 16)
+#define RG_HDMITX_PLL_BAND GENMASK(21, 16)
#define RG_HDMITX_PLL_REF_SEL BIT(15)
#define RG_HDMITX_PLL_BIAS_EN BIT(14)
#define RG_HDMITX_PLL_BIAS_LPF_EN BIT(13)
#define RG_HDMITX_PLL_TXDIV_EN BIT(12)
-#define RG_HDMITX_PLL_TXDIV (0x3 << 10)
+#define RG_HDMITX_PLL_TXDIV GENMASK(11, 10)
#define PLL_TXDIV_SHIFT 10
#define RG_HDMITX_PLL_LVROD_EN BIT(9)
#define RG_HDMITX_PLL_MONVC_EN BIT(8)
@@ -47,64 +47,64 @@
#define RG_HDMITX_PLL_MONREF_EN BIT(6)
#define RG_HDMITX_PLL_TST_EN BIT(5)
#define RG_HDMITX_PLL_TST_CK_EN BIT(4)
-#define RG_HDMITX_PLL_TST_SEL (0xf << 0)
+#define RG_HDMITX_PLL_TST_SEL GENMASK(3, 0)
#define HDMI_CON2 0x08
-#define RGS_HDMITX_PLL_AUTOK_BAND (0x7f << 8)
+#define RGS_HDMITX_PLL_AUTOK_BAND GENMASK(14, 8)
#define RGS_HDMITX_PLL_AUTOK_FAIL BIT(1)
#define RG_HDMITX_EN_TX_CKLDO BIT(0)
#define HDMI_CON3 0x0c
-#define RG_HDMITX_SER_EN (0xf << 28)
-#define RG_HDMITX_PRD_EN (0xf << 24)
-#define RG_HDMITX_PRD_IMP_EN (0xf << 20)
-#define RG_HDMITX_DRV_EN (0xf << 16)
-#define RG_HDMITX_DRV_IMP_EN (0xf << 12)
+#define RG_HDMITX_SER_EN GENMASK(31, 28)
+#define RG_HDMITX_PRD_EN GENMASK(27, 24)
+#define RG_HDMITX_PRD_IMP_EN GENMASK(23, 20)
+#define RG_HDMITX_DRV_EN GENMASK(19, 16)
+#define RG_HDMITX_DRV_IMP_EN GENMASK(15, 12)
#define DRV_IMP_EN_SHIFT 12
#define RG_HDMITX_MHLCK_FORCE BIT(10)
#define RG_HDMITX_MHLCK_PPIX_EN BIT(9)
#define RG_HDMITX_MHLCK_EN BIT(8)
-#define RG_HDMITX_SER_DIN_SEL (0xf << 4)
+#define RG_HDMITX_SER_DIN_SEL GENMASK(7, 4)
#define RG_HDMITX_SER_5T1_BIST_EN BIT(3)
#define RG_HDMITX_SER_BIST_TOG BIT(2)
#define RG_HDMITX_SER_DIN_TOG BIT(1)
#define RG_HDMITX_SER_CLKDIG_INV BIT(0)
#define HDMI_CON4 0x10
-#define RG_HDMITX_PRD_IBIAS_CLK (0xf << 24)
-#define RG_HDMITX_PRD_IBIAS_D2 (0xf << 16)
-#define RG_HDMITX_PRD_IBIAS_D1 (0xf << 8)
-#define RG_HDMITX_PRD_IBIAS_D0 (0xf << 0)
+#define RG_HDMITX_PRD_IBIAS_CLK GENMASK(27, 24)
+#define RG_HDMITX_PRD_IBIAS_D2 GENMASK(19, 16)
+#define RG_HDMITX_PRD_IBIAS_D1 GENMASK(11, 8)
+#define RG_HDMITX_PRD_IBIAS_D0 GENMASK(3, 0)
#define PRD_IBIAS_CLK_SHIFT 24
#define PRD_IBIAS_D2_SHIFT 16
#define PRD_IBIAS_D1_SHIFT 8
#define PRD_IBIAS_D0_SHIFT 0
#define HDMI_CON5 0x14
-#define RG_HDMITX_DRV_IBIAS_CLK (0x3f << 24)
-#define RG_HDMITX_DRV_IBIAS_D2 (0x3f << 16)
-#define RG_HDMITX_DRV_IBIAS_D1 (0x3f << 8)
-#define RG_HDMITX_DRV_IBIAS_D0 (0x3f << 0)
+#define RG_HDMITX_DRV_IBIAS_CLK GENMASK(29, 24)
+#define RG_HDMITX_DRV_IBIAS_D2 GENMASK(21, 16)
+#define RG_HDMITX_DRV_IBIAS_D1 GENMASK(13, 8)
+#define RG_HDMITX_DRV_IBIAS_D0 GENMASK(5, 0)
#define DRV_IBIAS_CLK_SHIFT 24
#define DRV_IBIAS_D2_SHIFT 16
#define DRV_IBIAS_D1_SHIFT 8
#define DRV_IBIAS_D0_SHIFT 0
#define HDMI_CON6 0x18
-#define RG_HDMITX_DRV_IMP_CLK (0x3f << 24)
-#define RG_HDMITX_DRV_IMP_D2 (0x3f << 16)
-#define RG_HDMITX_DRV_IMP_D1 (0x3f << 8)
-#define RG_HDMITX_DRV_IMP_D0 (0x3f << 0)
+#define RG_HDMITX_DRV_IMP_CLK GENMASK(29, 24)
+#define RG_HDMITX_DRV_IMP_D2 GENMASK(21, 16)
+#define RG_HDMITX_DRV_IMP_D1 GENMASK(13, 8)
+#define RG_HDMITX_DRV_IMP_D0 GENMASK(5, 0)
#define DRV_IMP_CLK_SHIFT 24
#define DRV_IMP_D2_SHIFT 16
#define DRV_IMP_D1_SHIFT 8
#define DRV_IMP_D0_SHIFT 0
#define HDMI_CON7 0x1c
-#define RG_HDMITX_MHLCK_DRV_IBIAS (0x1f << 27)
-#define RG_HDMITX_SER_DIN (0x3ff << 16)
-#define RG_HDMITX_CHLDC_TST (0xf << 12)
-#define RG_HDMITX_CHLCK_TST (0xf << 8)
-#define RG_HDMITX_RESERVE (0xff << 0)
+#define RG_HDMITX_MHLCK_DRV_IBIAS GENMASK(31, 27)
+#define RG_HDMITX_SER_DIN GENMASK(25, 16)
+#define RG_HDMITX_CHLDC_TST GENMASK(15, 12)
+#define RG_HDMITX_CHLCK_TST GENMASK(11, 8)
+#define RG_HDMITX_RESERVE GENMASK(7, 0)
#define HDMI_CON8 0x20
-#define RGS_HDMITX_2T1_LEV (0xf << 16)
-#define RGS_HDMITX_2T1_EDG (0xf << 12)
-#define RGS_HDMITX_5T1_LEV (0xf << 8)
-#define RGS_HDMITX_5T1_EDG (0xf << 4)
+#define RGS_HDMITX_2T1_LEV GENMASK(19, 16)
+#define RGS_HDMITX_2T1_EDG GENMASK(15, 12)
+#define RGS_HDMITX_5T1_LEV GENMASK(11, 8)
+#define RGS_HDMITX_5T1_EDG GENMASK(7, 4)
#define RGS_HDMITX_PLUG_TST BIT(0)
static int mtk_hdmi_pll_prepare(struct clk_hw *hw)
--
2.18.0
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next prev parent reply other threads:[~2022-09-20 9:04 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-20 9:00 [PATCH 00/18] unify register access and macros Chunfeng Yun
2022-09-20 9:00 ` [PATCH 01/18] phy: mediatek: add a new helper to update bitfield Chunfeng Yun
2022-09-21 8:15 ` AngeloGioacchino Del Regno
2022-09-22 2:36 ` Chunfeng Yun
2022-09-22 7:17 ` AngeloGioacchino Del Regno
2022-09-23 6:03 ` Chunfeng Yun
2022-09-20 9:00 ` [PATCH 02/18] phy: mediatek: tphy: remove macros to prepare bitfield value Chunfeng Yun
2022-09-20 9:00 ` [PATCH 03/18] phy: mediatek: xsphy: remove macros used " Chunfeng Yun
2022-09-20 9:00 ` [PATCH 04/18] phy: mediatek: ufs: use common register access helpers Chunfeng Yun
2022-09-21 8:13 ` AngeloGioacchino Del Regno
2022-09-20 9:00 ` [PATCH 05/18] phy: mediatek: pcie: use new helper to update register bits Chunfeng Yun
2022-09-21 8:13 ` AngeloGioacchino Del Regno
2022-09-20 9:00 ` [PATCH 06/18] phy: mediatek: hdmi: mt2701: use GENMASK and BIT to generate mask and bits Chunfeng Yun
2022-09-21 8:13 ` AngeloGioacchino Del Regno
2022-09-20 9:00 ` [PATCH 07/18] phy: mediatek: hdmi: mt2701: use FIELD_PREP to prepare bits field Chunfeng Yun
2022-09-21 8:13 ` AngeloGioacchino Del Regno
2022-09-20 9:00 ` [PATCH 08/18] phy: mediatek: hdmi: mt2701: use common helper to access registers Chunfeng Yun
2022-09-21 8:13 ` AngeloGioacchino Del Regno
2022-09-20 9:00 ` Chunfeng Yun [this message]
2022-09-21 8:13 ` [PATCH 09/18] phy: mediatek: hdmi: mt8173: use GENMASK to generate bits mask AngeloGioacchino Del Regno
2022-09-20 9:00 ` [PATCH 10/18] phy: mediatek: hdmi: mt8173: use FIELD_PREP to prepare bits field Chunfeng Yun
2022-09-21 8:13 ` AngeloGioacchino Del Regno
2022-09-20 9:00 ` [PATCH 11/18] phy: mediatek: hdmi: mt8173: use common helper to access registers Chunfeng Yun
2022-09-21 8:14 ` AngeloGioacchino Del Regno
2022-09-20 9:00 ` [PATCH 12/18] phy: mediatek: hdmi: remove register access helpers Chunfeng Yun
2022-09-21 8:13 ` AngeloGioacchino Del Regno
2022-09-20 9:00 ` [PATCH 13/18] phy: mediatek: mipi: mt8173: use GENMASK to generate bits mask Chunfeng Yun
2022-09-21 8:13 ` AngeloGioacchino Del Regno
2022-09-20 9:00 ` [PATCH 14/18] phy: mediatek: mipi: mt8173: use FIELD_PREP to prepare bits field Chunfeng Yun
2022-09-21 8:14 ` AngeloGioacchino Del Regno
2022-09-20 9:00 ` [PATCH 15/18] phy: mediatek: mipi: mt8173: use common helper to access registers Chunfeng Yun
2022-09-21 8:14 ` AngeloGioacchino Del Regno
2022-09-20 9:00 ` [PATCH 16/18] phy: mediatek: mipi: mt8183: use GENMASK to generate bits mask Chunfeng Yun
2022-09-21 8:14 ` AngeloGioacchino Del Regno
2022-09-20 9:00 ` [PATCH 17/18] phy: mediatek: mipi: mt8183: use common helper to access registers Chunfeng Yun
2022-09-21 8:14 ` AngeloGioacchino Del Regno
2022-09-20 9:00 ` [PATCH 18/18] phy: mediatek: mipi: remove register access helpers Chunfeng Yun
2022-09-21 8:15 ` AngeloGioacchino Del Regno
2022-09-24 6:28 ` [PATCH 00/18] unify register access and macros Vinod Koul
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