From: Robin Murphy <robin.murphy@arm.com>
To: will@kernel.org
Cc: robh@kernel.org, tomeu.vizoso@collabora.com,
narmstrong@baylibre.com, joro@8bytes.org, steven.price@arm.com,
iommu@lists.linux-foundation.org,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 2/3] iommu/io-pgtable-arm: Support all Mali configurations
Date: Mon, 30 Sep 2019 15:11:01 +0100 [thread overview]
Message-ID: <20e142e236decbed1b890ef455c5a1ddbdb48b9d.1569851517.git.robin.murphy@arm.com> (raw)
In-Reply-To: <cover.1569851517.git.robin.murphy@arm.com>
In principle, Midgard GPUs supporting smaller VA sizes should only
require 3-level pagetables, since level 0 only resolves bits 48:40 of
the address. However, the kbase driver does not appear to have any
notion of a variable start level, and empirically T720 and T820 rapidly
blow up with translation faults unless given a full 4-level table,
despite only supporting a 33-bit VA size.
The 'real' IAS value is still valuable in terms of validating addresses
on map/unmap, so tweak the allocator to allow smaller values while still
forcing the resultant tables to the full 4 levels. As far as I can test,
this should make all known Midgard variants happy.
Fixes: d08d42de6432 ("iommu: io-pgtable: Add ARM Mali midgard MMU page table format")
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Steven Price <steven.price@arm.com>
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
---
drivers/iommu/io-pgtable-arm.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c
index 90cb37af761c..ca51036aa53c 100644
--- a/drivers/iommu/io-pgtable-arm.c
+++ b/drivers/iommu/io-pgtable-arm.c
@@ -1024,7 +1024,7 @@ arm_mali_lpae_alloc_pgtable(struct io_pgtable_cfg *cfg, void *cookie)
if (cfg->quirks)
return NULL;
- if (cfg->ias != 48 || cfg->oas > 40)
+ if (cfg->ias > 48 || cfg->oas > 40)
return NULL;
cfg->pgsize_bitmap &= (SZ_4K | SZ_2M | SZ_1G);
@@ -1033,6 +1033,11 @@ arm_mali_lpae_alloc_pgtable(struct io_pgtable_cfg *cfg, void *cookie)
if (!data)
return NULL;
+ /* Mali seems to need a full 4-level table regardless of IAS */
+ if (data->levels < ARM_LPAE_MAX_LEVELS) {
+ data->levels = ARM_LPAE_MAX_LEVELS;
+ data->pgd_size = sizeof(arm_lpae_iopte);
+ }
/*
* MEMATTR: Mali has no actual notion of a non-cacheable type, so the
* best we can do is mimic the out-of-tree driver and hope that the
--
2.21.0.dirty
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next prev parent reply other threads:[~2019-09-30 14:11 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-30 14:10 [PATCH v2 0/3] iommu/io-pgtable-arm: Mali LPAE improvements Robin Murphy
2019-09-30 14:11 ` [PATCH v2 1/3] iommu/io-pgtable-arm: Correct Mali attributes Robin Murphy
2019-09-30 18:35 ` Rob Herring
2019-09-30 14:11 ` Robin Murphy [this message]
2019-09-30 18:36 ` [PATCH v2 2/3] iommu/io-pgtable-arm: Support all Mali configurations Rob Herring
2019-09-30 14:11 ` [PATCH v2 3/3] iommu/io-pgtable-arm: Allow coherent walks for Mali Robin Murphy
2019-09-30 18:36 ` Rob Herring
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