Re: [PATCH v2 18/20] arm64: dts: nuvoton: Add initial NPCM8XX device tree

From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Geert Uytterhoeven <geert@linux-m68k.org>,
	Tomer Maimon <tmaimon77@gmail.com>
Cc: "Avi Fishman" <avifishman70@gmail.com>,
	"Tali Perry" <tali.perry1@gmail.com>,
	"Joel Stanley" <joel@jms.id.au>,
	"Patrick Venture" <venture@google.com>,
	"Nancy Yuen" <yuenn@google.com>,
	"Benjamin Fair" <benjaminfair@google.com>,
	"Rob Herring" <robh+dt@kernel.org>,
	"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
	"Michael Turquette" <mturquette@baylibre.com>,
	"Stephen Boyd" <sboyd@kernel.org>,
	"Philipp Zabel" <p.zabel@pengutronix.de>,
	"Greg KH" <gregkh@linuxfoundation.org>,
	"Daniel Lezcano" <daniel.lezcano@linaro.org>,
	"Thomas Gleixner" <tglx@linutronix.de>,
	"Wim Van Sebroeck" <wim@linux-watchdog.org>,
	"Guenter Roeck" <linux@roeck-us.net>,
	"Catalin Marinas" <catalin.marinas@arm.com>,
	"Will Deacon" <will@kernel.org>, "Arnd Bergmann" <arnd@arndb.de>,
	"Olof Johansson" <olof@lixom.net>,
	"Jiri Slaby" <jirislaby@kernel.org>,
	"Shawn Guo" <shawnguo@kernel.org>,
	"Bjorn Andersson" <bjorn.andersson@linaro.org>,
	"Geert Uytterhoeven" <geert+renesas@glider.be>,
	"Marcel Ziswiler" <marcel.ziswiler@toradex.com>,
	"Vinod Koul" <vkoul@kernel.org>,
	"Biju Das" <biju.das.jz@bp.renesas.com>,
	"Nobuhiro Iwamatsu" <nobuhiro1.iwamatsu@toshiba.co.jp>,
	"Robert Hancock" <robert.hancock@calian.com>,
	"Jonathan Neuschäfer" <j.neuschaefer@gmx.net>,
	"Lubomir Rintel" <lkundrak@v3.sk>,
	devicetree <devicetree@vger.kernel.org>,
	"Linux Kernel Mailing List" <linux-kernel@vger.kernel.org>,
	linux-clk <linux-clk@vger.kernel.org>,
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	LINUXWATCHDOG <linux-watchdog@vger.kernel.org>,
	"Linux ARM" <linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH v2 18/20] arm64: dts: nuvoton: Add initial NPCM8XX device tree
Date: Fri, 10 Jun 2022 11:59:47 +0200	[thread overview]
Message-ID: <2f386fc3-d496-62e3-20b0-ac962169e7a1@linaro.org> (raw)
In-Reply-To: <CAMuHMdU53RWvKXd0cPcPA8SiMA820stcpK4_UsTDGDAfByhcYg@mail.gmail.com>

On 10/06/2022 09:57, Geert Uytterhoeven wrote:
>>  "+             cpu0: cpu@0 {
>>  +                     device_type = "cpu";
>>  +                     compatible = "arm,cortex-a35";
>>  +                     clocks = <&clk NPCM8XX_CLK_CPU>;
>>  +                     reg = <0x0 0x0>;
>> Why do you have two address cells? A bit more complicated and not
>> necessary, I think."
>> the arm,cortex-a35 is 64 Bit this is why we use  #address-cells = <2>;
>> and therefore reg = <0x0 0x0>;
> 
> These addresses are not addresses on the main memory bus (which
> is indeed 64-bit), but on the logical CPU bus.
> Now, Documentation/devicetree/bindings/arm/cpus.yaml says you can
> have #address-cells = <2> if you have non-zero MPIDR_EL1 high bits.
> 

Thanks Tomer and Geert for explanation. OK for me.

Best regards,
Krzysztof

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