From: Michal Simek <michal.simek@xilinx.com>
To: Alvaro Gamez Machado <alvaro.gamez@hazent.com>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Michal Simek <michal.simek@xilinx.com>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH] ARM: zynq: add flash memory interfaces, Xilinx efuse and missing clocks
Date: Tue, 14 Jan 2020 13:18:01 +0100 [thread overview]
Message-ID: <55db7dc3-ca06-4b01-417d-0b6869cb475a@xilinx.com> (raw)
In-Reply-To: <20200114120024.19779-1-alvaro.gamez@hazent.com>
Hi Alvaro,
here is missing description.
On 14. 01. 20 13:00, Alvaro Gamez Machado wrote:
> Signed-off-by: Alvaro Gamez Machado <alvaro.gamez@hazent.com>
> ---
> arch/arm/boot/dts/zynq-7000.dtsi | 50 ++++++++++++++++++++++++++++++--
> 1 file changed, 47 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
> index ca6425ad794c..8358315d7803 100644
> --- a/arch/arm/boot/dts/zynq-7000.dtsi
> +++ b/arch/arm/boot/dts/zynq-7000.dtsi
> @@ -197,6 +197,45 @@ spi1: spi@e0007000 {
> #size-cells = <0>;
> };
>
> + qspi: spi@e000d000 {
> + clock-names = "ref_clk", "pclk";
> + clocks = <&clkc 10>, <&clkc 43>;
> + compatible = "xlnx,zynq-qspi-1.0";
> + status = "disabled";
> + interrupt-parent = <&intc>;
> + interrupts = <0 19 4>;
> + reg = <0xe000d000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + smcc: memory-controller@e000e000 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + status = "disabled";
> + clock-names = "memclk", "apb_pclk";
> + clocks = <&clkc 11>, <&clkc 44>;
> + compatible = "arm,pl353-smc-r2p1", "arm,primecell";
> + interrupt-parent = <&intc>;
> + interrupts = <0 18 4>;
> + ranges ;
> + reg = <0xe000e000 0x1000>;
> + nand0: flash@e1000000 {
> + status = "disabled";
> + compatible = "arm,pl353-nand-r2p1";
note: Driver is not in mainline but dt binding has been reviewed already.
> + reg = <0xe1000000 0x1000000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + };
> + nor0: flash@e2000000 {
> + status = "disabled";
> + compatible = "cfi-flash";
> + reg = <0xe2000000 0x2000000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + };
> + };
> +
> gem0: ethernet@e000b000 {
> compatible = "cdns,zynq-gem", "cdns,gem";
> reg = <0xe000b000 0x1000>;
> @@ -297,14 +336,19 @@ dmac_s: dmac@f8003000 {
>
> devcfg: devcfg@f8007000 {
> compatible = "xlnx,zynq-devcfg-1.0";
> - reg = <0xf8007000 0x100>;
> interrupt-parent = <&intc>;
> interrupts = <0 8 4>;
> - clocks = <&clkc 12>;
> - clock-names = "ref_clk";
> + reg = <0xf8007000 0x100>;
> + clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;
> + clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";
This is not the part of dt binding.
> syscon = <&slcr>;
> };
>
> + efuse: efuse@f800d000 {
> + compatible = "xlnx,zynq-efuse";
> + reg = <0xf800d000 0x20>;
> + };
ditto.
> +
> global_timer: timer@f8f00200 {
> compatible = "arm,cortex-a9-global-timer";
> reg = <0xf8f00200 0x20>;
>
Thanks,
Michal
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prev parent reply other threads:[~2020-01-14 12:18 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-14 12:00 [PATCH] ARM: zynq: add flash memory interfaces, Xilinx efuse and missing clocks Alvaro Gamez Machado
2020-01-14 12:18 ` Michal Simek [this message]
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