From: Rex-BC Chen <rex-bc.chen@mediatek.com>
To: Nancy.Lin <nancy.lin@mediatek.com>,
Rob Herring <robh+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
Chun-Kuang Hu <chunkuang.hu@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>, <wim@linux-watchdog.org>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>, <linux@roeck-us.net>
Cc: David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
"Nathan Chancellor" <nathan@kernel.org>,
Nick Desaulniers <ndesaulniers@google.com>,
"jason-jh . lin" <jason-jh.lin@mediatek.com>,
Yongqiang Niu <yongqiang.niu@mediatek.com>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-mediatek@lists.infradead.org>,
<dri-devel@lists.freedesktop.org>, <llvm@lists.linux.dev>,
<singo.chang@mediatek.com>, <srv_heupstream@mediatek.com>,
<Project_Global_Chrome_Upstream_Group@mediatek.com>
Subject: Re: [PATCH v15 04/22] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1
Date: Thu, 17 Mar 2022 21:01:07 +0800 [thread overview]
Message-ID: <5c21b7c1606cf635123791c3e0c3a8a0cb8889c6.camel@mediatek.com> (raw)
In-Reply-To: <20220311015506.11232-5-nancy.lin@mediatek.com>
On Fri, 2022-03-11 at 09:54 +0800, Nancy.Lin wrote:
> Add mt8195 vdosys1 clock driver name and routing table to
> the driver data of mtk-mmsys.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> ---
> drivers/soc/mediatek/mt8195-mmsys.h | 136
> +++++++++++++++++++++++++
> drivers/soc/mediatek/mtk-mmsys.c | 10 ++
> include/linux/soc/mediatek/mtk-mmsys.h | 2 +
> 3 files changed, 148 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mt8195-mmsys.h
> b/drivers/soc/mediatek/mt8195-mmsys.h
> index 24a3afe23bc8..369fb0aab56d 100644
> --- a/drivers/soc/mediatek/mt8195-mmsys.h
> +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> @@ -75,6 +75,70 @@
> #define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 <<
> 16)
> #define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE
> (3 << 16)
>
> +#define MT8195_VDO1_VPP_MERGE0_P0_SEL_IN 0xf04
> +#define MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0
> 1
> +
> +#define MT8195_VDO1_VPP_MERGE0_P1_SEL_IN 0xf08
> +#define MT8195_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1
> 1
> +
> +#define MT8195_VDO1_DISP_DPI1_SEL_IN 0xf10
> +#define MT8195_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT
> 0
> +
> +#define MT8195_VDO1_DISP_DP_INTF0_SEL_IN 0xf14
> +#define MT8195_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT
> 0
> +
> +#define MT8195_VDO1_MERGE4_SOUT_SEL 0xf18
> +#define MT8195_MERGE4_SOUT_TO_DPI1_SEL
> 2
> +#define MT8195_MERGE4_SOUT_TO_DP_INTF0_SEL
> 3
> +
> +#define MT8195_VDO1_MIXER_IN1_SEL_IN 0xf24
> +#define MT8195_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT
> 1
> +
> +#define MT8195_VDO1_MIXER_IN2_SEL_IN 0xf28
> +#define MT8195_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT
> 1
> +
> +#define MT8195_VDO1_MIXER_IN3_SEL_IN 0xf2c
> +#define MT8195_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT
> 1
> +
> +#define MT8195_VDO1_MIXER_IN4_SEL_IN 0xf30
> +#define MT8195_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT
> 1
> +
> +#define MT8195_VDO1_MIXER_OUT_SOUT_SEL
> 0xf34
> +#define MT8195_MIXER_SOUT_TO_MERGE4_ASYNC_SEL
> 1
> +
> +#define MT8195_VDO1_VPP_MERGE1_P0_SEL_IN 0xf3c
> +#define MT8195_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2
> 1
> +
> +#define MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL 0xf40
> +#define MT8195_SOUT_TO_MIXER_IN1_SEL
> 1
> +
> +#define MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL 0xf44
> +#define MT8195_SOUT_TO_MIXER_IN2_SEL
> 1
> +
> +#define MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL 0xf48
> +#define MT8195_SOUT_TO_MIXER_IN3_SEL
> 1
> +
> +#define MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL 0xf4c
> +#define MT8195_SOUT_TO_MIXER_IN4_SEL
> 1
> +
> +#define MT8195_VDO1_MERGE4_ASYNC_SEL_IN
> 0xf50
> +#define MT8195_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT
> 1
> +
> +#define MT8195_VDO1_MIXER_IN1_SOUT_SEL
> 0xf58
> +#define MT8195_MIXER_IN1_SOUT_TO_DISP_MIXER
> 0
> +
> +#define MT8195_VDO1_MIXER_IN2_SOUT_SEL
> 0xf5c
> +#define MT8195_MIXER_IN2_SOUT_TO_DISP_MIXER
> 0
> +
> +#define MT8195_VDO1_MIXER_IN3_SOUT_SEL
> 0xf60
> +#define MT8195_MIXER_IN3_SOUT_TO_DISP_MIXER
> 0
> +
> +#define MT8195_VDO1_MIXER_IN4_SOUT_SEL
> 0xf64
> +#define MT8195_MIXER_IN4_SOUT_TO_DISP_MIXER
> 0
> +
> +#define MT8195_VDO1_MIXER_SOUT_SEL_IN
> 0xf68
> +#define MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER
> 0
> +
> static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] =
> {
> {
> DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
> @@ -124,6 +188,78 @@ static const struct mtk_mmsys_routes
> mmsys_mt8195_routing_table[] = {
> DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
> MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> MT8195_SOUT_VPP_MERGE_TO_DP_INTF0
> + }, {
> + DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
> + MT8195_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0),
> + MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0
> + }, {
> + DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
> + MT8195_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0),
> + MT8195_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1
> + }, {
> + DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
> + MT8195_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0),
> + MT8195_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2
> + }, {
> + DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
> + MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0),
> + MT8195_SOUT_TO_MIXER_IN1_SEL
> + }, {
> + DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
> + MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0),
> + MT8195_SOUT_TO_MIXER_IN2_SEL
> + }, {
> + DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
> + MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0),
> + MT8195_SOUT_TO_MIXER_IN3_SEL
> + }, {
> + DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
> + MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0),
> + MT8195_SOUT_TO_MIXER_IN4_SEL
> + }, {
> + DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
> + MT8195_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0),
> + MT8195_MIXER_SOUT_TO_MERGE4_ASYNC_SEL
> + }, {
> + DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
> + MT8195_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0),
> + MT8195_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT
> + }, {
> + DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
> + MT8195_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0),
> + MT8195_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT
> + }, {
> + DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
> + MT8195_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0),
> + MT8195_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT
> + }, {
> + DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
> + MT8195_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0),
> + MT8195_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT
> + }, {
> + DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
> + MT8195_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0),
> + MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER
> + }, {
> + DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
> + MT8195_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0),
> + MT8195_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT
> + }, {
> + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
> + MT8195_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0),
> + MT8195_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT
> + }, {
> + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
> + MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0),
> + MT8195_MERGE4_SOUT_TO_DPI1_SEL
> + }, {
> + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
> + MT8195_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0),
> + MT8195_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT
> + }, {
> + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
> + MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0),
> + MT8195_MERGE4_SOUT_TO_DP_INTF0_SEL
> }
> };
>
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> b/drivers/soc/mediatek/mtk-mmsys.c
> index dc5c51f0ccc8..0b77624cf6ca 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -79,6 +79,12 @@ static const struct mtk_mmsys_driver_data
> mt8195_vdosys0_driver_data = {
> .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> };
>
> +static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data
> = {
> + .clk_driver = "clk-mt8195-vdo1",
> + .routes = mmsys_mt8195_routing_table,
> + .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> +};
> +
> static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data =
> {
> .clk_driver = "clk-mt8365-mm",
> .routes = mt8365_mmsys_routing_table,
> @@ -271,6 +277,10 @@ static const struct of_device_id
> of_match_mtk_mmsys[] = {
> .compatible = "mediatek,mt8195-vdosys0",
> .data = &mt8195_vdosys0_driver_data,
> },
> + {
> + .compatible = "mediatek,mt8195-vdosys1",
> + .data = &mt8195_vdosys1_driver_data,
> + },
> {
> .compatible = "mediatek,mt8365-mmsys",
> .data = &mt8365_mmsys_driver_data,
> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h
> b/include/linux/soc/mediatek/mtk-mmsys.h
> index 64c77c4a6c56..eaf7f7345519 100644
> --- a/include/linux/soc/mediatek/mtk-mmsys.h
> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> @@ -18,6 +18,7 @@ enum mtk_ddp_comp_id {
> DDP_COMPONENT_COLOR1,
> DDP_COMPONENT_DITHER,
> DDP_COMPONENT_DP_INTF0,
> + DDP_COMPONENT_DP_INTF1,
> DDP_COMPONENT_DPI0,
> DDP_COMPONENT_DPI1,
> DDP_COMPONENT_DSC0,
> @@ -39,6 +40,7 @@ enum mtk_ddp_comp_id {
> DDP_COMPONENT_OVL_2L0,
> DDP_COMPONENT_OVL_2L1,
> DDP_COMPONENT_OVL_2L2,
> + DDP_COMPONENT_OVL_ADAPTOR,
> DDP_COMPONENT_OVL1,
> DDP_COMPONENT_POSTMASK0,
> DDP_COMPONENT_PWM0,
_______________________________________________
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next prev parent reply other threads:[~2022-03-17 13:12 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-11 1:54 [PATCH v15 00/22] Add MediaTek SoC DRM (vdosys1) support for mt8195 Nancy.Lin
2022-03-11 1:54 ` [PATCH v15 01/22] dt-bindings: mediatek: add vdosys1 RDMA definition " Nancy.Lin
2022-03-11 9:31 ` AngeloGioacchino Del Regno
2022-03-11 1:54 ` [PATCH v15 02/22] dt-bindings: reset: mt8195: add vdosys1 reset control bit Nancy.Lin
2022-03-11 1:54 ` [PATCH v15 03/22] dt-bindings: mediatek: add ethdr definition for mt8195 Nancy.Lin
2022-03-11 1:54 ` [PATCH v15 04/22] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1 Nancy.Lin
2022-03-17 13:01 ` Rex-BC Chen [this message]
2022-03-11 1:54 ` [PATCH v15 05/22] soc: mediatek: add mtk-mmsys config API " Nancy.Lin
2022-03-11 1:54 ` [PATCH v15 06/22] soc: mediatek: add cmdq support of " Nancy.Lin
2022-03-11 1:54 ` [PATCH v15 07/22] soc: mediatek: mmsys: modify reset controller for MT8195 vdosys1 Nancy.Lin
2022-03-11 1:54 ` [PATCH v15 08/22] soc: mediatek: change the mutex defines and the mutex_mod type Nancy.Lin
2022-03-11 1:54 ` [PATCH v15 09/22] soc: mediatek: add mtk-mutex support for mt8195 vdosys1 Nancy.Lin
2022-03-11 1:54 ` [PATCH v15 10/22] drm/mediatek: add display MDP RDMA support for MT8195 Nancy.Lin
2022-03-11 1:54 ` [PATCH v15 11/22] drm/mediatek: add display merge advance config API " Nancy.Lin
2022-03-11 1:54 ` [PATCH v15 12/22] drm/mediatek: add display merge start/stop API for cmdq support Nancy.Lin
2022-03-11 1:54 ` [PATCH v15 13/22] drm/mediatek: add display merge mute/unmute support for MT8195 Nancy.Lin
2022-03-11 1:54 ` [PATCH v15 14/22] drm/mediatek: add display merge async reset control Nancy.Lin
2022-03-11 1:54 ` [PATCH v15 15/22] drm/mediatek: add ETHDR support for MT8195 Nancy.Lin
2022-03-11 1:55 ` [PATCH v15 16/22] drm/mediatek: add mediatek-drm plane color encoding info Nancy.Lin
2022-03-11 1:55 ` [PATCH v15 17/22] drm/mediatek: add ovl_adaptor support for MT8195 Nancy.Lin
2022-03-11 1:55 ` [PATCH v15 18/22] drm/mediatek: add dma dev get function Nancy.Lin
2022-03-11 1:55 ` [PATCH v15 19/22] drm/mediatek: modify mediatek-drm for mt8195 multi mmsys support Nancy.Lin
2022-03-14 10:08 ` CK Hu
2022-03-18 13:04 ` Nancy.Lin
2022-03-11 1:55 ` [PATCH v15 20/22] drm/mediatek: add drm ovl_adaptor sub driver for MT8195 Nancy.Lin
2022-03-15 5:08 ` CK Hu
2022-03-18 13:05 ` Nancy.Lin
2022-03-11 1:55 ` [PATCH v15 21/22] drm/mediatek: add mediatek-drm of vdosys1 support " Nancy.Lin
2022-03-15 5:10 ` CK Hu
2022-03-18 13:06 ` Nancy.Lin
2022-03-11 1:55 ` [PATCH v15 22/22] arm64: dts: mt8195: add display node for vdosys1 Nancy.Lin
2022-03-11 9:51 ` [PATCH v15 00/22] Add MediaTek SoC DRM (vdosys1) support for mt8195 AngeloGioacchino Del Regno
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