From: Anshuman Khandual <anshuman.khandual@arm.com>
To: Suzuki K Poulose <suzuki.poulose@arm.com>,
linux-arm-kernel@lists.infradead.org
Cc: mark.rutland@arm.com, catalin.marinas@arm.com,
linux-kernel@vger.kernel.org, james.morse@arm.com,
maz@kernel.org, will@kernel.org
Subject: Re: [PATCH 6/6] arm64/cpufeature: Replace all open bits shift encodings with macros
Date: Thu, 2 Apr 2020 08:14:32 +0530 [thread overview]
Message-ID: <5d331165-6d3f-55d3-8994-d736d5fdb3ef@arm.com> (raw)
In-Reply-To: <caea646f-2a74-115b-ab03-fb1325ed101f@arm.com>
On 03/21/2020 12:10 AM, Suzuki K Poulose wrote:
> On 01/28/2020 12:39 PM, Anshuman Khandual wrote:
>> There are many open bits shift encodings for various CPU ID registers that
>> are scattered across cpufeature. This replaces them with register specific
>> sensible macro definitions. This should not have any functional change.
>>
>> Cc: Catalin Marinas <catalin.marinas@arm.com>
>> Cc: Will Deacon <will@kernel.org>
>> Cc: Marc Zyngier <maz@kernel.org>
>> Cc: Mark Rutland <mark.rutland@arm.com>
>> Cc: James Morse <james.morse@arm.com>
>> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
>> Cc: linux-kernel@vger.kernel.org
>> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
>> ---
>
>
>> --- a/arch/arm64/kernel/cpufeature.c
>> +++ b/arch/arm64/kernel/cpufeature.c
>> @@ -263,7 +263,7 @@ static const struct arm64_ftr_bits ftr_ctr[] = {
>> * make use of *minLine.
>> * If we have differing I-cache policies, report it as the weakest - VIPT.
>> */
>> - ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, 14, 2, ICACHE_POLICY_VIPT), /* L1Ip */
>> + ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_L1IP_SHIFT, 2, ICACHE_POLICY_VIPT), /* L1Ip */
>> ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0),
>> ARM64_FTR_END,
>> };
>> @@ -274,19 +274,19 @@ struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
>> };
>> static const struct arm64_ftr_bits ftr_it will not be a good idea to id_mmfr0[] = {
>> - S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0xf), /* InnerShr */
>> - ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), /* FCSE */
>> - ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0), /* AuxReg */
>> - ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), /* TCM */
>> - ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), /* ShareLvl */
>> - S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0xf), /* OuterShr */
>> - ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* PMSA */
>> - ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* VMSA */
>> + S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_INNERSHR_SHIFT, 4, 0xf),
>> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_FCSE_SHIFT, 4, 0),
>> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_AUXREG_SHIFT, 4, 0),
>> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_TCM_SHIFT, 4, 0),
>> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_SHARELVL_SHIFT, 4, 0),
>> + S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_OUTERSHR_SHIFT, 4, 0xf),
>> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_PMSA_SHIFT, 4, 0),
>> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_VMSA_SHIFT, 4, 0),
>> ARM64_FTR_END,
>> };
>> static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
>> - ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 36, 28, 0),
>> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DOUBLELOCK_SHIFT, 28, 0),
>
> This must be a signed feature, as we have the following possible values :
>
> 0b0000 - Double lock implemented
> 0b1111 - Double lock not implemented.
>
> So, in case of a conflict we want the safe value as 0b1111.
>
> Please could you fix this as well ?
Sure but in a separate patch, as would like to prevent mixing any
actual code change from macro replacement.
>
>
> This patch as such looks fine to me.
>
> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
>
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next prev parent reply other threads:[~2020-04-02 2:44 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-28 12:39 [PATCH 0/6] Introduce ID_PFR2 and other CPU feature changes Anshuman Khandual
2020-01-28 12:39 ` [PATCH 1/6] arm64/cpufeature: Introduce ID_PFR2 CPU register Anshuman Khandual
2020-03-20 18:03 ` Suzuki K Poulose
2020-04-09 12:54 ` Will Deacon
2020-04-13 3:32 ` Anshuman Khandual
2020-01-28 12:39 ` [PATCH 2/6] arm64/cpufeature: Add DIT and CSV2 feature bits in ID_PFR0 register Anshuman Khandual
2020-03-20 18:07 ` Suzuki K Poulose
2020-04-02 2:38 ` Anshuman Khandual
2020-04-09 12:55 ` Will Deacon
2020-04-13 3:35 ` Anshuman Khandual
2020-01-28 12:39 ` [PATCH 3/6] arm64/cpufeature: Add remaining feature bits in ID_MMFR4 register Anshuman Khandual
2020-03-20 18:11 ` Suzuki K Poulose
2020-04-02 2:38 ` Anshuman Khandual
2020-01-28 12:39 ` [PATCH 4/6] arm64/cpufeature: Define an explicit ftr_id_isar0[] for ID_ISAR0 register Anshuman Khandual
2020-03-20 18:16 ` Suzuki K Poulose
2020-01-28 12:39 ` [PATCH 5/6] arm64/cpufeature: Drop TraceFilt feature exposure from ID_DFR0 register Anshuman Khandual
2020-03-20 18:19 ` Suzuki K Poulose
2020-04-02 3:00 ` Anshuman Khandual
2020-04-09 12:53 ` Will Deacon
2020-04-13 3:39 ` Anshuman Khandual
2020-01-28 12:39 ` [PATCH 6/6] arm64/cpufeature: Replace all open bits shift encodings with macros Anshuman Khandual
2020-03-20 18:40 ` Suzuki K Poulose
2020-04-02 2:44 ` Anshuman Khandual [this message]
2020-02-14 4:23 ` [PATCH 0/6] Introduce ID_PFR2 and other CPU feature changes Anshuman Khandual
2020-02-14 15:58 ` Peter Maydell
2020-04-02 2:33 ` Anshuman Khandual
2020-03-20 18:49 ` Suzuki K Poulose
2020-04-06 17:09 ` Will Deacon
2020-04-07 8:50 ` Anshuman Khandual
2020-04-09 13:54 ` Will Deacon
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