From: Lukasz Luba <l.luba@partner.samsung.com>
To: Chanwoo Choi <cw00.choi@samsung.com>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org
Cc: Mark Rutland <mark.rutland@arm.com>,
b.zolnierkie@samsung.com, krzk@kernel.org,
Rob Herring <robh+dt@kernel.org>,
kyungmin.park@samsung.com, kgene@kernel.org,
myungjoo.ham@samsung.com, s.nawrocki@samsung.com,
linux-arm-kernel@lists.infradead.org, m.szyprowski@samsung.com
Subject: Re: [PATCH v3 1/8] clk: samsung: add needed IDs for DMC clocks in Exynos5420
Date: Fri, 1 Feb 2019 14:49:23 +0100 [thread overview]
Message-ID: <66b886d3-37af-dc54-9dd8-c56977709e2a@partner.samsung.com> (raw)
In-Reply-To: <d6124295-cb72-0d5f-f887-438698cf48e1@samsung.com>
Hi Chanwoo,
On 2/1/19 8:40 AM, Chanwoo Choi wrote:
> Hi,
>
> On 19. 1. 31. 오후 5:49, Lukasz Luba wrote:
>> Define new IDs for clocks used by Dynamic Memory Controller in
>> Exynos5422 SoC.
>>
>> CC: Sylwester Nawrocki <s.nawrocki@samsung.com>
>> CC: Chanwoo Choi <cw00.choi@samsung.com>
>> CC: Rob Herring <robh+dt@kernel.org>
>> CC: Mark Rutland <mark.rutland@arm.com>
>> CC: Kukjin Kim <kgene@kernel.org>
>> CC: Krzysztof Kozlowski <krzk@kernel.org>
>> CC: linux-samsung-soc@vger.kernel.org
>> CC: devicetree@vger.kernel.org
>> CC: linux-arm-kernel@lists.infradead.org
>> CC: linux-kernel@vger.kernel.org
>> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
>> ---
>> include/dt-bindings/clock/exynos5420.h | 18 +++++++++++++++++-
>> 1 file changed, 17 insertions(+), 1 deletion(-)
>>
>> diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h
>> index 355f469..1827a64 100644
>> --- a/include/dt-bindings/clock/exynos5420.h
>> +++ b/include/dt-bindings/clock/exynos5420.h
>> @@ -60,6 +60,7 @@
>> #define CLK_MAU_EPLL 159
>> #define CLK_SCLK_HSIC_12M 160
>> #define CLK_SCLK_MPHY_IXTAL24 161
>> +#define CLK_SCLK_BPLL 162
>>
>> /* gate clocks */
>> #define CLK_UART0 257
>> @@ -195,6 +196,16 @@
>> #define CLK_ACLK432_CAM 518
>> #define CLK_ACLK_FL1550_CAM 519
>> #define CLK_ACLK550_CAM 520
>> +#define CLK_CLKM_PHY0 521
>> +#define CLK_CLKM_PHY1 522
>> +#define CLK_ACLK_PPMU_DREX0_0 523
>> +#define CLK_ACLK_PPMU_DREX0_1 524
>> +#define CLK_ACLK_PPMU_DREX1_0 525
>> +#define CLK_ACLK_PPMU_DREX1_1 526
>> +#define CLK_PCLK_PPMU_DREX0_0 527
>> +#define CLK_PCLK_PPMU_DREX0_1 528
>> +#define CLK_PCLK_PPMU_DREX1_0 529
>> +#define CLK_PCLK_PPMU_DREX1_1 530
>>
>> /* mux clocks */
>> #define CLK_MOUT_HDMI 640
>> @@ -217,6 +228,10 @@
>> #define CLK_MOUT_EPLL 657
>> #define CLK_MOUT_MAU_EPLL 658
>> #define CLK_MOUT_USER_MAU_EPLL 659
>> +#define CLK_MOUT_DPLL 660
>> +#define CLK_MOUT_ACLK_G3D 661
>
> The second patch don't implement some clocks
> for CLK_MOUT_DPLL, CLK_MOUT_ACLK_G3D.
>
> Why do you define them?
You are right, it is a mistake.
I will remove it in v2.
Regards,
Lukasz
>
> (snip)
>
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next prev parent reply other threads:[~2019-02-01 13:49 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <1548924594-19084-1-git-send-email-l.luba@partner.samsung.com>
[not found] ` <CGME20190131085006eucas1p2e4ba3f69e039c394e7cd42389ac8bfa7@eucas1p2.samsung.com>
2019-01-31 8:49 ` [PATCH v3 1/8] clk: samsung: add needed IDs for DMC clocks in Exynos5420 Lukasz Luba
2019-02-01 7:40 ` Chanwoo Choi
2019-02-01 13:49 ` Lukasz Luba [this message]
[not found] ` <CGME20190131085006eucas1p1ca478545c107086d427909c88d3b232e@eucas1p1.samsung.com>
2019-01-31 8:49 ` [PATCH v3 2/8] clk: samsung: add new clocks for DMC for Exynos5422 SoC Lukasz Luba
2019-02-01 8:07 ` Chanwoo Choi
2019-02-01 9:20 ` Chanwoo Choi
2019-02-01 13:03 ` Lukasz Luba
[not found] ` <CGME20190131085007eucas1p2f16107042b8ce5638811840618bcf017@eucas1p2.samsung.com>
2019-01-31 8:49 ` [PATCH v3 3/8] clk: samsung: add BPLL rate table for Exynos 5422 SoC Lukasz Luba
2019-02-01 8:44 ` Chanwoo Choi
2019-02-01 13:56 ` Lukasz Luba
2019-02-01 14:19 ` Sylwester Nawrocki
2019-02-01 15:39 ` Lukasz Luba
2019-02-03 7:54 ` Chanwoo Choi
2019-02-11 10:21 ` Lukasz Luba
2019-02-11 10:34 ` Chanwoo Choi
[not found] ` <CGME20190131085008eucas1p237fe9e2f8cb6254e8da7c97c2984e6b2@eucas1p2.samsung.com>
2019-01-31 8:49 ` [PATCH v3 4/8] drivers: devfreq: add DMC driver for Exynos5422 Lukasz Luba
[not found] ` <CGME20190131085009eucas1p14c96bc345bc4c414e6c4d7506f14e69c@eucas1p1.samsung.com>
2019-01-31 8:49 ` [PATCH v3 5/8] dt-bindings: devfreq: add Exynos5422 DMC device description Lukasz Luba
[not found] ` <CGME20190131085009eucas1p166467551006e54130905ebb5eefdefab@eucas1p1.samsung.com>
2019-01-31 8:49 ` [PATCH v3 6/8] DT: arm: exynos: add DMC device for exynos5422 Lukasz Luba
[not found] ` <CGME20190131085010eucas1p2b2bdc90be27dfd73f13d41ed0d725bb2@eucas1p2.samsung.com>
2019-01-31 8:49 ` [PATCH v3 7/8] drivers: devfreq: events: add Exynos PPMU new events Lukasz Luba
[not found] ` <CGME20190131085011eucas1p2c315d69c8902fbceff689f3a92e0c5d9@eucas1p2.samsung.com>
2019-01-31 8:49 ` [PATCH v3 8/8] ARM: exynos_defconfig: enable DMC driver Lukasz Luba
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