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From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: mike.leach@linaro.org
Cc: coresight@lists.linaro.org, anshuman.khandual@arm.com,
	mathieu.poirier@linaro.org, linux-arm-kernel@lists.infradead.org,
	leo.yan@linaro.org
Subject: Re: [PATCH 15/19] coresight: etm4x: Use TRCDEVARCH for component discovery
Date: Tue, 22 Sep 2020 12:18:29 +0100	[thread overview]
Message-ID: <7b0c27e5-6391-b8d2-fcdb-97cb26bc398b@arm.com> (raw)
In-Reply-To: <CAJ9a7VhYpuuuVAvAuQLukijTEeX8w+OnV34eH1nLxO0fBPdQ2g@mail.gmail.com>

On 09/18/2020 04:35 PM, Mike Leach wrote:
> Hi Suzuki
> 
> On Fri, 11 Sep 2020 at 09:41, Suzuki K Poulose <suzuki.poulose@arm.com> wrote:
>>
>> We have been using TRCIDR1 for detecting the ETM version. As
>> we are about to discover the trace unit on a CPU, let us use a
>> CoreSight architected register, instead of an ETM architected
>> register for accurate detection on a CPU. e.g, a CPU might
>> implement a custom trace unit, not an ETM.
>>
>> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>


>>   static int etm4_cpu_id(struct coresight_device *csdev)
>>   {
>>          struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
>> @@ -694,10 +693,23 @@ static void etm_detect_lock_status(struct etmv4_drvdata *drvdata,
>>          drvdata->os_lock_model = TRCOSLSR_OSM(os_lsr);
>>   }
>>
>> +static inline bool trace_unit_supported(u32 devarch)
>> +{
>> +       return (devarch & ETM_DEVARCH_ID_MASK) == ETM_DEVARCH_ETMv4x_ARCH;
>> +}
>> +
> 
> This is fine for system reg access - but imposes additional
> constraints on memory mapped devices that previously may have worked
> just by matching CID/PID. Can you be certain there are no devices out
> there that have omitted this register (it does have a present bit
> after all)

Very good point and I agree. I could restrict this to system instruction
based devices and use the TRCIDR1 for

> 
>>   static bool etm_init_iomem_access(struct etmv4_drvdata *drvdata,
>>                                    struct csdev_access *csa)
>>   {
>> +       u32 devarch;
>> +
>> +       devarch = readl_relaxed(drvdata->base + TRCDEVARCH);
>> +       if (!trace_unit_supported(devarch))
>> +               return false;
>> +
>>          *csa = CSDEV_ACCESS_IOMEM(drvdata->base);
>> +       drvdata->arch = devarch;
>> +
>>          return true;
>>   }
>>
>> @@ -713,7 +725,6 @@ static bool etm_init_csdev_access(struct etmv4_drvdata *drvdata,
>>   static void etm4_init_arch_data(void *info)
> 
> The primary task of this routine is to read all the ID registers and
> set up the data in regards to resources etc.
> We should not be mixing in a secondary task of detection of a valid device.

I agree that we have to read up the registers. However, for system instructions
based devices, we shouldn't try to access random register space, if they are not
ETM. Moreover, it kind of simplifies the logic, where you don't have to read up
all the registers if this is not a supported device in the first place.

Or the other way around, I think the priority is to make sure we are dealing with
a valid device we support, before we tread into reading the register space to avoid
unknown side effects of the operations.

Thanks

Suzuki

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  reply	other threads:[~2020-09-22 11:15 UTC|newest]

Thread overview: 54+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-09-11  8:41 [PATCH 00/19] coresight: Support for ETMv4.4 system instructions Suzuki K Poulose
2020-09-11  8:41 ` [PATCH 01/19] coresight: Introduce device access abstraction Suzuki K Poulose
2020-09-18 15:33   ` Mike Leach
2020-09-11  8:41 ` [PATCH 02/19] coresight: tpiu: Prepare for using coresight " Suzuki K Poulose
2020-09-18 15:34   ` Mike Leach
2020-09-11  8:41 ` [PATCH 03/19] coresight: Convert coresight_timeout to use " Suzuki K Poulose
2020-09-18 15:34   ` Mike Leach
2020-09-11  8:41 ` [PATCH 04/19] coresight: Convert claim/disclaim operations to use access wrappers Suzuki K Poulose
2020-09-18 15:34   ` Mike Leach
2020-09-11  8:41 ` [PATCH 05/19] coresight: Use device access layer for Software lock/unlock operations Suzuki K Poulose
2020-09-18 15:34   ` Mike Leach
2020-09-18 15:52     ` Suzuki K Poulose
2020-09-11  8:41 ` [PATCH 06/19] coresight: etm4x: Always read the registers on the host CPU Suzuki K Poulose
2020-09-18 15:34   ` Mike Leach
2020-09-11  8:41 ` [PATCH 07/19] coresight: etm4x: Convert all register accesses Suzuki K Poulose
2020-09-18 15:34   ` Mike Leach
2020-09-11  8:41 ` [PATCH 08/19] coresight: etm4x: Add commentary on the registers Suzuki K Poulose
2020-09-18 15:34   ` Mike Leach
2020-09-11  8:41 ` [PATCH 09/19] coresight: etm4x: Add sysreg access helpers Suzuki K Poulose
2020-09-18 15:34   ` Mike Leach
2020-09-11  8:41 ` [PATCH 10/19] coresight: etm4x: Define DEVARCH register fields Suzuki K Poulose
2020-09-18 15:34   ` Mike Leach
2020-09-22 10:20     ` Suzuki K Poulose
2020-09-11  8:41 ` [PATCH 11/19] coresight: etm4x: Check for OS and Software Lock Suzuki K Poulose
2020-09-18 15:35   ` Mike Leach
2020-09-22 10:44     ` Suzuki K Poulose
2020-09-11  8:41 ` [PATCH 12/19] coresight: etm4x: Cleanup secure exception level masks Suzuki K Poulose
2020-09-18 15:35   ` Mike Leach
2020-09-22 10:55     ` Suzuki K Poulose
2020-09-22 12:47       ` Mike Leach
2020-09-30 10:32         ` Suzuki K Poulose
2020-09-11  8:41 ` [PATCH 13/19] coresight: etm4x: Clean up " Suzuki K Poulose
2020-09-18 15:35   ` Mike Leach
2020-09-22 10:59     ` Suzuki K Poulose
2020-09-11  8:41 ` [PATCH 14/19] coresight: etm4x: Detect access early on the target CPU Suzuki K Poulose
2020-09-11  8:41 ` [PATCH 15/19] coresight: etm4x: Use TRCDEVARCH for component discovery Suzuki K Poulose
2020-09-18 15:35   ` Mike Leach
2020-09-22 11:18     ` Suzuki K Poulose [this message]
2020-09-11  8:41 ` [PATCH 16/19] coresight: etm4x: Detect system instructions support Suzuki K Poulose
2020-09-18 15:35   ` Mike Leach
2020-09-22 11:59     ` Suzuki K Poulose
2020-09-11  8:41 ` [PATCH 17/19] coresight: etm4x: Refactor probing routine Suzuki K Poulose
2020-09-18 15:35   ` Mike Leach
2020-09-11  8:41 ` [PATCH 18/19] coresight: etm4x: Add support for sysreg only devices Suzuki K Poulose
2020-09-18 15:35   ` Mike Leach
2020-09-23 11:52     ` Suzuki K Poulose
2020-09-23 16:55       ` Mike Leach
2020-09-11  8:41 ` [PATCH 19/19] dts: bindings: coresight: ETMv4.4 system register access only units Suzuki K Poulose
2020-09-18 15:35   ` Mike Leach
2020-09-24  9:48     ` Suzuki K Poulose
2020-09-24 10:08       ` Mike Leach
2020-09-18 15:33 ` [PATCH 00/19] coresight: Support for ETMv4.4 system instructions Mike Leach
2020-09-25  9:55   ` Suzuki K Poulose
2020-09-29 16:42     ` Mike Leach

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