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Mon, 08 Feb 2021 11:36:09 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l94pq-0000yW-Oe for linux-arm-kernel@lists.infradead.org; Mon, 08 Feb 2021 11:36:07 +0000 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 3C3BB60231; Mon, 8 Feb 2021 11:36:05 +0000 (UTC) Received: from 78.163-31-62.static.virginmediabusiness.co.uk ([62.31.163.78] helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94) (envelope-from ) id 1l94pn-00ClWO-1g; Mon, 08 Feb 2021 11:36:03 +0000 Date: Mon, 08 Feb 2021 11:36:02 +0000 Message-ID: <87a6selrkt.wl-maz@kernel.org> From: Marc Zyngier To: Arnd Bergmann Subject: Re: [PATCH 15/18] irqchip/apple-aic: Add support for the Apple Interrupt Controller In-Reply-To: References: <20210204203951.52105-1-marcan@marcan.st> <20210204203951.52105-16-marcan@marcan.st> <87eehqlxlr.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: arnd@kernel.org, marcan@marcan.st, soc@kernel.org, linux-arm-kernel@lists.infradead.org, robh+dt@kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, olof@lixom.net X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210208_063606_943163_9000B700 X-CRM114-Status: GOOD ( 21.55 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , List-Id: Cc: DTML , Hector Martin , "linux-kernel@vger.kernel.org" , SoC Team , Rob Herring , Olof Johansson , Linux ARM Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, 08 Feb 2021 10:29:23 +0000, Arnd Bergmann wrote: > > On Mon, Feb 8, 2021 at 10:25 AM Marc Zyngier wrote: > > On Thu, 04 Feb 2021 20:39:48 +0000, Hector Martin wrote: > > > > +{ > > > + return readl(ic->base + reg); > > > > Please consider using the _relaxed accessors, as I don't think any of > > these interacts with memory (apart from IPIs, of course). > > MSI interrupts require serializing with DMA, so at the minimum I think there > needs to be something that ensures that DMA from device into memory > has completed before delivering the completion interrupt to a driver. This > may already be implied when the AIC is entered, but this is hard to know > without actual hardware specs. If there is a sync with memory required, it should happen at the point where it is Acked, not when masked/unmasked or anything else. And given that you want to sync with an external agent (the DMA producer), the DMB generated by readl won't save you, as it only orders CPU accesses AFAICT. So if MSIs require some additional synchronisation we probably need a DSB somewhere if the HW doesn't guarantee ordering of DMA vs MSIs. Whether it does or not is anyone's bet. Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel