From: "André Przywara" <andre.przywara@arm.com>
To: Icenowy Zheng <icenowy@aosc.io>,
Maxime Ripard <mripard@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
Jernej Skrabec <jernej.skrabec@siol.net>
Cc: Philipp Zabel <p.zabel@pengutronix.de>,
Stephen Boyd <sboyd@kernel.org>,
Linus Walleij <linus.walleij@linaro.org>,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
linux-sunxi@googlegroups.com, Rob Herring <robh+dt@kernel.org>,
Icenowy Zheng <icenowy@aosc.xyz>,
Yangtao Li <frank@allwinnertech.com>,
Michael Turquette <mturquette@baylibre.com>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 4/8] clk: sunxi-ng: Add support for the Allwinner H616 R-CCU
Date: Thu, 3 Dec 2020 11:07:02 +0000 [thread overview]
Message-ID: <94f2b2db-cffd-06d5-f660-eed07b5cafe6@arm.com> (raw)
In-Reply-To: <422A0729-7E7C-4ABF-BEAB-21772FDD0CE3@aosc.io>
On 02/12/2020 14:31, Icenowy Zheng wrote:
Hi,
> 于 2020年12月2日 GMT+08:00 下午9:54:05, Andre Przywara <andre.przywara@arm.com> 写到:
>> The clocks itself are identical to the H6 R-CCU, it's just that the
>> H616
>> has not all of them implemented (or connected).
>
> For selective clocks, try to follow the practice of V3(s) driver?
Not sure what you mean, isn't that what I do? Having a separate
sunxi_ccu_desc for each SoC and referencing separate structs? At least
that's what I see in ccu-sun8i-v3s.c.
What am I missing?
Cheers,
Andre
>>
>> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
>> ---
>> drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 47 +++++++++++++++++++++++++-
>> drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h | 3 +-
>> 2 files changed, 48 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
>> b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
>> index 50f8d1bc7046..119d1797f501 100644
>> --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
>> +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
>> @@ -136,6 +136,15 @@ static struct ccu_common *sun50i_h6_r_ccu_clks[] =
>> {
>> &w1_clk.common,
>> };
>>
>> +static struct ccu_common *sun50i_h616_r_ccu_clks[] = {
>> + &r_apb1_clk.common,
>> + &r_apb2_clk.common,
>> + &r_apb1_twd_clk.common,
>> + &r_apb2_i2c_clk.common,
>> + &r_apb1_ir_clk.common,
>> + &ir_clk.common,
>> +};
>> +
>> static struct clk_hw_onecell_data sun50i_h6_r_hw_clks = {
>> .hws = {
>> [CLK_AR100] = &ar100_clk.common.hw,
>> @@ -152,7 +161,20 @@ static struct clk_hw_onecell_data
>> sun50i_h6_r_hw_clks = {
>> [CLK_IR] = &ir_clk.common.hw,
>> [CLK_W1] = &w1_clk.common.hw,
>> },
>> - .num = CLK_NUMBER,
>> + .num = CLK_NUMBER_H616,
>> +};
>> +
>> +static struct clk_hw_onecell_data sun50i_h616_r_hw_clks = {
>> + .hws = {
>> + [CLK_R_AHB] = &r_ahb_clk.hw,
>> + [CLK_R_APB1] = &r_apb1_clk.common.hw,
>> + [CLK_R_APB2] = &r_apb2_clk.common.hw,
>> + [CLK_R_APB1_TWD] = &r_apb1_twd_clk.common.hw,
>> + [CLK_R_APB2_I2C] = &r_apb2_i2c_clk.common.hw,
>> + [CLK_R_APB1_IR] = &r_apb1_ir_clk.common.hw,
>> + [CLK_IR] = &ir_clk.common.hw,
>> + },
>> + .num = CLK_NUMBER_H616,
>> };
>>
>> static struct ccu_reset_map sun50i_h6_r_ccu_resets[] = {
>> @@ -165,6 +187,12 @@ static struct ccu_reset_map
>> sun50i_h6_r_ccu_resets[] = {
>> [RST_R_APB1_W1] = { 0x1ec, BIT(16) },
>> };
>>
>> +static struct ccu_reset_map sun50i_h616_r_ccu_resets[] = {
>> + [RST_R_APB1_TWD] = { 0x12c, BIT(16) },
>> + [RST_R_APB2_I2C] = { 0x19c, BIT(16) },
>> + [RST_R_APB1_IR] = { 0x1cc, BIT(16) },
>> +};
>> +
>> static const struct sunxi_ccu_desc sun50i_h6_r_ccu_desc = {
>> .ccu_clks = sun50i_h6_r_ccu_clks,
>> .num_ccu_clks = ARRAY_SIZE(sun50i_h6_r_ccu_clks),
>> @@ -175,6 +203,16 @@ static const struct sunxi_ccu_desc
>> sun50i_h6_r_ccu_desc = {
>> .num_resets = ARRAY_SIZE(sun50i_h6_r_ccu_resets),
>> };
>>
>> +static const struct sunxi_ccu_desc sun50i_h616_r_ccu_desc = {
>> + .ccu_clks = sun50i_h616_r_ccu_clks,
>> + .num_ccu_clks = ARRAY_SIZE(sun50i_h616_r_ccu_clks),
>> +
>> + .hw_clks = &sun50i_h616_r_hw_clks,
>> +
>> + .resets = sun50i_h616_r_ccu_resets,
>> + .num_resets = ARRAY_SIZE(sun50i_h616_r_ccu_resets),
>> +};
>> +
>> static void __init sunxi_r_ccu_init(struct device_node *node,
>> const struct sunxi_ccu_desc *desc)
>> {
>> @@ -195,3 +233,10 @@ static void __init sun50i_h6_r_ccu_setup(struct
>> device_node *node)
>> }
>> CLK_OF_DECLARE(sun50i_h6_r_ccu, "allwinner,sun50i-h6-r-ccu",
>> sun50i_h6_r_ccu_setup);
>> +
>> +static void __init sun50i_h616_r_ccu_setup(struct device_node *node)
>> +{
>> + sunxi_r_ccu_init(node, &sun50i_h616_r_ccu_desc);
>> +}
>> +CLK_OF_DECLARE(sun50i_h616_r_ccu, "allwinner,sun50i-h616-r-ccu",
>> + sun50i_h616_r_ccu_setup);
>> diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h
>> b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h
>> index 782117dc0b28..128302696ca1 100644
>> --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h
>> +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h
>> @@ -14,6 +14,7 @@
>>
>> #define CLK_R_APB2 3
>>
>> -#define CLK_NUMBER (CLK_W1 + 1)
>> +#define CLK_NUMBER_H6 (CLK_W1 + 1)
>> +#define CLK_NUMBER_H616 (CLK_IR + 1)
>>
>> #endif /* _CCU_SUN50I_H6_R_H */
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next prev parent reply other threads:[~2020-12-03 11:09 UTC|newest]
Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-02 13:54 [PATCH 0/8] arm64: sunxi: Initial Allwinner H616 SoC support Andre Przywara
2020-12-02 13:54 ` [PATCH 1/8] clk: sunxi-ng: h6: Fix clock divider range on some clocks Andre Przywara
2020-12-02 16:17 ` Jernej Škrabec
2020-12-02 13:54 ` [PATCH 2/8] pinctrl: sunxi: Add support for the Allwinner H616 pin controller Andre Przywara
2020-12-02 15:52 ` Maxime Ripard
2020-12-05 22:41 ` Linus Walleij
2020-12-02 18:15 ` Jernej Škrabec
2020-12-06 12:32 ` [linux-sunxi] " Clément Péron
2020-12-06 12:42 ` Jernej Škrabec
2020-12-06 14:52 ` André Przywara
2020-12-06 16:01 ` Icenowy Zheng
2020-12-07 1:07 ` André Przywara
2020-12-07 1:45 ` André Przywara
2020-12-13 16:27 ` Icenowy Zheng
2020-12-14 9:26 ` Chen-Yu Tsai
2020-12-02 13:54 ` [PATCH 3/8] pinctrl: sunxi: Add support for the Allwinner H616-R " Andre Przywara
2020-12-02 15:54 ` Maxime Ripard
2020-12-02 17:55 ` Jernej Škrabec
2020-12-02 13:54 ` [PATCH 4/8] clk: sunxi-ng: Add support for the Allwinner H616 R-CCU Andre Przywara
2020-12-02 14:31 ` Icenowy Zheng
2020-12-03 11:07 ` André Przywara [this message]
2020-12-03 14:02 ` [linux-sunxi] " Icenowy Zheng
2020-12-02 18:20 ` Jernej Škrabec
2020-12-03 2:44 ` Samuel Holland
2020-12-03 10:52 ` André Przywara
2020-12-02 13:54 ` [PATCH 5/8] clk: sunxi-ng: Add support for the Allwinner H616 CCU Andre Przywara
2020-12-02 15:56 ` Maxime Ripard
2020-12-02 21:03 ` Jernej Škrabec
2020-12-02 23:06 ` André Przywara
2020-12-05 16:36 ` [linux-sunxi] " Icenowy Zheng
2020-12-09 14:33 ` [linux-sunxi] " Clément Péron
2020-12-09 21:35 ` André Przywara
2020-12-09 22:20 ` Jernej Škrabec
2020-12-09 22:45 ` André Przywara
2020-12-10 13:31 ` Icenowy Zheng
2020-12-10 14:34 ` André Przywara
2020-12-02 13:54 ` [PATCH 6/8] mmc: sunxi: add support for A100 mmc controller Andre Przywara
2020-12-02 13:54 ` [PATCH 7/8] arm64: dts: allwinner: Add Allwinner H616 .dtsi file Andre Przywara
2020-12-02 16:03 ` Icenowy Zheng
2020-12-02 16:19 ` André Przywara
2020-12-02 16:05 ` Maxime Ripard
2020-12-02 16:13 ` Icenowy Zheng
2020-12-03 3:10 ` Samuel Holland
2020-12-02 16:33 ` Jernej Škrabec
2020-12-03 1:35 ` André Przywara
2020-12-03 3:16 ` Samuel Holland
2020-12-03 10:53 ` André Przywara
2020-12-03 15:02 ` [linux-sunxi] " Chen-Yu Tsai
2020-12-03 15:44 ` André Przywara
2020-12-03 16:20 ` Chen-Yu Tsai
2020-12-08 0:47 ` André Przywara
2020-12-02 13:54 ` [PATCH 8/8] arm64: dts: allwinner: Add OrangePi Zero 2 .dts Andre Przywara
2020-12-02 15:57 ` Icenowy Zheng
2020-12-02 16:43 ` André Przywara
2020-12-02 16:07 ` Maxime Ripard
2020-12-02 16:25 ` Jernej Škrabec
2020-12-06 12:51 ` [linux-sunxi] " Clément Péron
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