From: "Koenig, Christian" <Christian.Koenig@amd.com>
To: Benjamin Herrenschmidt <benh@kernel.crashing.org>,
Michael Ellerman <mpe@ellerman.id.au>,
Will Deacon <will.deacon@arm.com>
Cc: "Carsten Haitzler" <Carsten.Haitzler@arm.com>,
"Ard Biesheuvel" <ard.biesheuvel@linaro.org>,
"David Airlie" <airlied@linux.ie>,
"Michel Dänzer" <michel@daenzer.net>,
"Linux Kernel Mailing List" <linux-kernel@vger.kernel.org>,
dri-devel <dri-devel@lists.freedesktop.org>,
"Huang, Ray" <Ray.Huang@amd.com>,
"Zhang, Jerry" <Jerry.Zhang@amd.com>,
linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
"Bernhard Rosenkränzer" <Bernhard.Rosenkranzer@linaro.org>
Subject: Re: [RFC PATCH] drm/ttm: force cached mappings for system RAM on ARM
Date: Wed, 16 Jan 2019 07:35:58 +0000 [thread overview]
Message-ID: <9dc27cbf-e109-0c32-fc92-6fce1b224cda@amd.com> (raw)
In-Reply-To: <ed2dd9042d1afede4843d7fd3728a4d701a19fdd.camel@kernel.crashing.org>
Am 16.01.19 um 01:33 schrieb Benjamin Herrenschmidt:
> On Tue, 2019-01-15 at 22:31 +1100, Michael Ellerman wrote:
>>>> As far as I know Power doesn't really supports un-cached memory at all,
>>>> except for a very very old and odd configuration with AGP.
>>> Hopefully Michael/Ben can elaborate here, but I was under the (possibly
>>> mistaken) impression that mismatched attributes could cause a machine-check
>>> on Power.
>> That's what I've always been told, but I can't actually find where it's
>> documented, I'll keep searching.
>>
>> But you're right that mixing cached / uncached is not really supported,
>> and probably results in a machine check or worse.
> .. or worse :) It could checkstop.
Not sure if that would be so bad, it would at least give us a clear
indicator that something is wrong instead of silently corrupting data.
> It's also my understanding that on ARM v7 and above, it's technically
> forbidden to map the same physical page with both cached and non-cached
> mappings, since the cached one could prefetch (or speculatively load),
> thus creating collisions and inconsistencies. Am I wrong here ?
No, but you answer the wrong question.
See we don't want to have different mappings of cached and non-cached on
the CPU, but rather want to know if a snooped DMA from the PCIe counts
as cached access as well.
As far as I know on x86 it doesn't, so when you have an un-cached page
you can still access it with a snooping DMA read/write operation and
don't cause trouble.
> The old hack of using non-cached mapping to avoid snoop cost in AGP and
> others is just that ... an ugly and horrible hacks that should have
> never eventuated, when the search for performance pushes HW people into
> utter insanity :)
Well I agree that un-cached system memory makes things much more
complicated for a questionable gain.
But fact is we now have to deal with the mess, so no point in
complaining about it to much :)
Cheers,
Christian.
>
> Cheers,
> Ben.
>
>
>
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next prev parent reply other threads:[~2019-01-16 7:36 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-10 7:28 [RFC PATCH] drm/ttm: force cached mappings for system RAM on ARM Ard Biesheuvel
2019-01-10 8:36 ` Zhang, Jerry(Junwei)
2019-01-10 8:36 ` Koenig, Christian
2019-01-10 9:34 ` Michel Dänzer
2019-01-14 10:53 ` Ard Biesheuvel
2019-01-14 11:38 ` Koenig, Christian
2019-01-14 17:32 ` Ard Biesheuvel
[not found] ` <9f956898-7973-98ee-6bf1-e1d445e9d365@amd.com>
2019-01-14 19:13 ` Will Deacon
2019-01-14 19:21 ` Koenig, Christian
2019-01-14 19:35 ` Will Deacon
2019-01-15 11:31 ` Michael Ellerman
2019-01-16 0:33 ` Benjamin Herrenschmidt
2019-01-16 7:35 ` Koenig, Christian [this message]
2019-01-16 7:47 ` Ard Biesheuvel
2019-01-17 6:07 ` Benjamin Herrenschmidt
2019-01-17 8:02 ` Ard Biesheuvel
2019-01-17 5:59 ` Benjamin Herrenschmidt
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