From: "Wong, Vee Khee" <vee.khee.wong@intel.com>
To: "Voon, Weifeng" <weifeng.voon@intel.com>,
"David S . Miller" <davem@davemloft.net>,
Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: "netdev@vger.kernel.org" <netdev@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Jose Abreu <joabreu@synopsys.com>,
Jakub Kicinski <kuba@kernel.org>,
Giuseppe Cavallaro <peppe.cavallaro@st.com>,
Alexandre Torgue <alexandre.torgue@st.com>,
"linux-stm32@st-md-mailman.stormreply.com"
<linux-stm32@st-md-mailman.stormreply.com>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"Ong, Boon Leong" <boon.leong.ong@intel.com>
Subject: RE: [PATCH net-next] net: intel: Enable SERDES PHY rx clk for PSE
Date: Mon, 5 Apr 2021 18:06:16 +0000 [thread overview]
Message-ID: <BYAPR11MB28702C161D1C95E0D5C3A64AAB779@BYAPR11MB2870.namprd11.prod.outlook.com> (raw)
In-Reply-To: <20210405163357.30902-1-weifeng.voon@intel.com>
On Tue, Apr 06, 2021 at 12:33:57AM +0800, Voon Weifeng wrote:
>
> EHL PSE SGMII mode requires to ungate the SERDES PHY rx clk for power up
> sequence and vice versa.
>
> Signed-off-by: Voon Weifeng <weifeng.voon@intel.com>
> ---
> drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c | 10 ++++++++++
> drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h | 1 +
> 2 files changed, 11 insertions(+)
>
Why not use "stmmac: intel" for the commit message header?
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
> b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
> index add95e20548d..a4fec5fe0779 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
> @@ -153,6 +153,11 @@ static int intel_serdes_powerup(struct net_device
> *ndev, void *priv_data)
> return data;
> }
>
> + /* PSE only - ungate SGMII PHY Rx Clock */
> + if (intel_priv->is_pse)
> + mdiobus_modify(priv->mii, serdes_phy_addr, SERDES_GCR0,
> + 0, SERDES_PHY_RX_CLK);
> +
> return 0;
> }
>
> @@ -168,6 +173,11 @@ static void intel_serdes_powerdown(struct
> net_device *ndev, void *intel_data)
>
> serdes_phy_addr = intel_priv->mdio_adhoc_addr;
>
> + /* PSE only - gate SGMII PHY Rx Clock */
> + if (intel_priv->is_pse)
> + mdiobus_modify(priv->mii, serdes_phy_addr, SERDES_GCR0,
> + SERDES_PHY_RX_CLK, 0);
> +
> /* move power state to P3 */
> data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
>
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h
> b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h
> index e723096c0b15..542acb8ce467 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h
> @@ -14,6 +14,7 @@
>
> /* SERDES defines */
> #define SERDES_PLL_CLK BIT(0) /* PLL clk valid signal
> */
> +#define SERDES_PHY_RX_CLK BIT(1) /* PSE SGMII PHY rx clk */
> #define SERDES_RST BIT(2) /* Serdes Reset */
> #define SERDES_PWR_ST_MASK GENMASK(6, 4) /* Serdes Power
> state*/
> #define SERDES_PWR_ST_SHIFT 4
> --
> 2.17.1
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prev parent reply other threads:[~2021-04-05 18:08 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-05 16:33 [PATCH net-next] net: intel: Enable SERDES PHY rx clk for PSE Voon Weifeng
2021-04-05 18:06 ` Wong, Vee Khee [this message]
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