Re: [PATCH 11/16] dt-bindings: clock: renesas: Document RZ/G2L SoC CPG driver

From: Geert Uytterhoeven <geert@linux-m68k.org>
To: "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
Cc: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
	 Rob Herring <robh+dt@kernel.org>,
	Magnus Damm <magnus.damm@gmail.com>,
	 Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	 Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Catalin Marinas <catalin.marinas@arm.com>,
	 Will Deacon <will@kernel.org>, Jiri Slaby <jirislaby@kernel.org>,
	 Philipp Zabel <p.zabel@pengutronix.de>,
	 "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
	<devicetree@vger.kernel.org>,
	 Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	 Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
	linux-clk <linux-clk@vger.kernel.org>,
	 "open list:SERIAL DRIVERS" <linux-serial@vger.kernel.org>,
	 Linux ARM <linux-arm-kernel@lists.infradead.org>,
	 Biju Das <biju.das.jz@bp.renesas.com>
Subject: Re: [PATCH 11/16] dt-bindings: clock: renesas: Document RZ/G2L SoC CPG driver
Date: Thu, 27 May 2021 13:51:34 +0200	[thread overview]
Message-ID: <CAMuHMdW0fihLr8_fOzvQ6=WjfR11T2K8UXsKrDCb4JvF79wM_w@mail.gmail.com> (raw)
In-Reply-To: <CA+V-a8u-dqrzsVfZ2MiBrANM+=RaBG=rZLcbG38Rc--wEpOaCg@mail.gmail.com>

Hi Prabhakar,

On Fri, May 21, 2021 at 8:43 PM Lad, Prabhakar
<prabhakar.csengg@gmail.com> wrote:
> On Fri, May 21, 2021 at 4:04 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > On Fri, May 14, 2021 at 9:23 PM Lad Prabhakar
> > <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> > > Document the device tree bindings of the Renesas RZ/G2L SoC clock
> > > driver in Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml.
> > >
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> >
> > Thanks for your patch!
> >
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
> > > @@ -0,0 +1,80 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > +%YAML 1.2
> > > +---
> > > +$id: "http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#"
> > > +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> > > +
> > > +title: Renesas RZ/G2L Clock Pulse Generator / Module Stop and Software Reset
> >
> > (Module Standby Mode
> > > +
> > > +maintainers:
> > > +  - Geert Uytterhoeven <geert+renesas@glider.be>
> > > +
> > > +description: |
> > > +  On Renesas RZ/G2L SoC, the CPG (Clock Pulse Generator) and MSTP
> > > +  (Module Stop and Software Reset) share the same register block.
> > > +
> > > +  They provide the following functionalities:
> > > +    - The CPG block generates various core clocks,
> > > +    - The MSTP block provides two functions:
> > > +        1. Module Stop, providing a Clock Domain to control the clock supply
> > > +           to individual SoC devices,
> > > +        2. Reset Control, to perform a software reset of individual SoC devices.
> > > +
> > > +properties:
> > > +  compatible:
> > > +    const: renesas,r9a07g044l-cpg  # RZ/G2L
> >
> > renesas,r9a07g044-cpg?
> >
> As some IP blocks present in RZ/G2L aren't present in RZ/G2LC clock
> handling will differ so as a result SoC specific compatible string is
> added.

The RZ/G2L Hardware User's Manual Rev. 0.41 doesn't mention any
differences between the CPG on RZ/G2L and RZ/G2LC.  So I think it's
safe to have a single driver for both members.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

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