From: leonard.crestez@nxp.com (Leonard Crestez)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 3/3] PCI: imx: Add support for i.MX8MQ
Date: Tue, 27 Nov 2018 10:46:44 +0000 [thread overview]
Message-ID: <VI1PR04MB5533DE497786CD80D4FE0941EED00@VI1PR04MB5533.eurprd04.prod.outlook.com> (raw)
In-Reply-To: 1543313169.2507.39.camel@pengutronix.de
On 11/27/18 12:06 PM, Lucas Stach wrote:
> Hi Andrey,
>
> Am Montag, den 26.11.2018, 10:24 -0800 schrieb Andrey Smirnov:
>> On Tue, Nov 20, 2018 at 2:49 AM Leonard Crestez <leonard.crestez@nxp.com> wrote:
>>>
>>> On Sat, 2018-11-17 at 10:12 -0800, Andrey Smirnov wrote:
>>>> @@ -921,7 +1004,28 @@ static int imx6_pcie_probe(struct platform_device *pdev)
>>>> -?????case IMX7D:
>>>> +?????case IMX8MQ:
>>>> +?????????????if (of_property_read_u32(node, "fsl,iomux-gpr1x",
>>>> +??????????????????????????????????????&imx6_pcie->gpr1x)) {
>>>> +?????????????????????dev_err(dev, "Failed to get GPR1x address\n");
>>>> +?????????????????????return -EINVAL;
>>>> +?????????????}
>>>
>>> This is for distinguishing multiple controllers on the SOC but other
>>> registers and bits might differ. Isn't it preferable to have a property
>>> for controller id instead of adding many registers to DT?
>>
>> I liked encoding necessary info in DT directly slightly better than
>> encoding abstract ID and then decoding it further in the driver code.
>> OTOH, I am not really attached to that path. Lucas, can you comment on
>> this please?
>
> Yes, after rereading the patch with this in mind I agree that having
> the GPR offset on DT directly is IMO the better approach than an
> abstract ID.
But it's not a single offset, for example the device_type (EP/RC) has
bits for the two controllers side-by-side in GPR12.
Adding a "ctrl-id" property would fully describe the hardware from the
start. If we add per-register information instead then when other
registers are used we'll get DT compatibility headaches.
It's worth noting that 8qm/8qxp also have multiple controllers with a
different set of bits placed differently in iomuxc.
next prev parent reply other threads:[~2018-11-27 10:46 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-17 18:12 [PATCH 0/3] PCIE support for i.MX8MQ Andrey Smirnov
2018-11-17 18:12 ` [PATCH 1/3] PCI: imx: No-op imx6_setup_phy_mpll() on i.MX7D Andrey Smirnov
2018-11-17 18:12 ` [PATCH 2/3] PCI: imx: No-op imx6_pcie_reset_phy() " Andrey Smirnov
2018-11-20 1:22 ` Trent Piepho
2018-11-26 18:32 ` Andrey Smirnov
2018-11-17 18:12 ` [PATCH 3/3] PCI: imx: Add support for i.MX8MQ Andrey Smirnov
2018-11-19 7:07 ` Richard Zhu
2018-11-26 18:09 ` Andrey Smirnov
2018-11-29 10:52 ` Richard Zhu
2018-11-20 10:48 ` Leonard Crestez
2018-11-26 18:24 ` Andrey Smirnov
2018-11-27 10:06 ` Lucas Stach
2018-11-27 10:46 ` Leonard Crestez [this message]
2018-11-27 21:14 ` Andrey Smirnov
2018-11-28 10:55 ` Leonard Crestez
2018-11-29 11:15 ` Lucas Stach
2018-11-29 11:12 ` Lucas Stach
2018-11-27 10:16 ` Leonard Crestez
2018-11-27 21:03 ` Andrey Smirnov
2018-12-03 12:20 ` [PATCH 0/3] PCIE " Lorenzo Pieralisi
2018-12-07 11:37 ` Lorenzo Pieralisi
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