From: abhinavk@codeaurora.org
To: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>,
Rob Clark <robdclark@gmail.com>, Sean Paul <sean@poorly.run>,
Jonathan Marek <jonathan@marek.ca>,
Stephen Boyd <sboyd@kernel.org>,
linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org,
David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
freedreno@lists.freedesktop.org
Subject: Re: [Freedreno] [PATCH v2 21/22] drm/msm/dpu: fix CDP setup to account for multirect index
Date: Tue, 09 Nov 2021 18:12:48 -0800 [thread overview]
Message-ID: <1fb08ef9aa4d5d2e7d76453386bd2b75@codeaurora.org> (raw)
In-Reply-To: <20210705012115.4179824-22-dmitry.baryshkov@linaro.org>
On 2021-07-04 18:21, Dmitry Baryshkov wrote:
> Client driven prefetch (CDP) is properly setup only for SSPP REC0
> currently. Enable client driven prefetch also for SSPP REC1.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 12 ++++++++++--
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 4 +++-
> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 2 +-
> 3 files changed, 14 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> index f93cdeb08ac7..96f2f3f12f34 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> @@ -75,6 +75,7 @@
> #define SSPP_TRAFFIC_SHAPER 0x130
> #define SSPP_CDP_CNTL 0x134
> #define SSPP_UBWC_ERROR_STATUS 0x138
> +#define SSPP_CDP_CNTL_REC1 0x13c
> #define SSPP_TRAFFIC_SHAPER_PREFILL 0x150
> #define SSPP_TRAFFIC_SHAPER_REC1_PREFILL 0x154
> #define SSPP_TRAFFIC_SHAPER_REC1 0x158
> @@ -624,10 +625,12 @@ static void dpu_hw_sspp_setup_qos_ctrl(struct
> dpu_hw_pipe *ctx,
> }
>
> static void dpu_hw_sspp_setup_cdp(struct dpu_hw_pipe *ctx,
> - struct dpu_hw_pipe_cdp_cfg *cfg)
> + struct dpu_hw_pipe_cdp_cfg *cfg,
> + enum dpu_sspp_multirect_index index)
> {
> u32 idx;
> u32 cdp_cntl = 0;
> + u32 cdp_cntl_offset = 0;
>
> if (!ctx || !cfg)
> return;
> @@ -635,6 +638,11 @@ static void dpu_hw_sspp_setup_cdp(struct
> dpu_hw_pipe *ctx,
> if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx))
> return;
>
> + if (index == DPU_SSPP_RECT_SOLO || index == DPU_SSPP_RECT_0)
> + cdp_cntl_offset = SSPP_CDP_CNTL;
> + else
> + cdp_cntl_offset = SSPP_CDP_CNTL_REC1;
> +
> if (cfg->enable)
> cdp_cntl |= BIT(0);
> if (cfg->ubwc_meta_enable)
> @@ -644,7 +652,7 @@ static void dpu_hw_sspp_setup_cdp(struct
> dpu_hw_pipe *ctx,
> if (cfg->preload_ahead == DPU_SSPP_CDP_PRELOAD_AHEAD_64)
> cdp_cntl |= BIT(3);
>
> - DPU_REG_WRITE(&ctx->hw, SSPP_CDP_CNTL, cdp_cntl);
> + DPU_REG_WRITE(&ctx->hw, cdp_cntl_offset, cdp_cntl);
> }
>
> static void _setup_layer_ops(struct dpu_hw_pipe *c,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
> index c5ac8defa073..19c5358b962c 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
> @@ -358,9 +358,11 @@ struct dpu_hw_sspp_ops {
> * setup_cdp - setup client driven prefetch
> * @ctx: Pointer to pipe context
> * @cfg: Pointer to cdp configuration
> + * @index: rectangle index in multirect
> */
> void (*setup_cdp)(struct dpu_hw_pipe *ctx,
> - struct dpu_hw_pipe_cdp_cfg *cfg);
> + struct dpu_hw_pipe_cdp_cfg *cfg,
> + enum dpu_sspp_multirect_index index);
> };
>
> /**
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> index d692136884ad..420cdd90e89b 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> @@ -1241,7 +1241,7 @@ static void dpu_plane_sspp_atomic_update(struct
> drm_plane *plane)
> DPU_FORMAT_IS_TILE(fmt);
> cdp_cfg.preload_ahead = DPU_SSPP_CDP_PRELOAD_AHEAD_64;
>
> - pstate->pipe_hw->ops.setup_cdp(pstate->pipe_hw, &cdp_cfg);
> + pstate->pipe_hw->ops.setup_cdp(pstate->pipe_hw, &cdp_cfg,
> pstate->multirect_index);
> }
> }
next prev parent reply other threads:[~2021-11-10 2:12 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-05 1:20 [PATCH v2 00/22] drm/msm/dpu: switch dpu_plane to be virtual Dmitry Baryshkov
2021-07-05 1:20 ` [PATCH v2 01/22] drm/msm/dpu: move LUT levels out of QOS config Dmitry Baryshkov
2021-07-05 1:20 ` [PATCH v2 02/22] drm/msm/dpu: remove pipe_qos_cfg from struct dpu_plane Dmitry Baryshkov
2021-07-05 1:20 ` [PATCH v2 03/22] drm/msm/dpu: drop pipe_name " Dmitry Baryshkov
2021-07-05 1:20 ` [PATCH v2 04/22] drm/msm/dpu: remove stage_cfg from struct dpu_crtc Dmitry Baryshkov
2021-07-05 1:20 ` [PATCH v2 05/22] drm/msm/dpu: rip out master planes support Dmitry Baryshkov
2021-07-05 1:20 ` [PATCH v2 06/22] drm/msm/dpu: move dpu_hw_pipe_cfg out of struct dpu_plane Dmitry Baryshkov
2021-07-05 1:21 ` [PATCH v2 07/22] drm/msm/dpu: drop scaler config from plane state Dmitry Baryshkov
2021-07-05 1:21 ` [PATCH v2 08/22] drm/msm/dpu: drop dpu_csc_cfg from dpu_plane Dmitry Baryshkov
2021-07-05 1:21 ` [PATCH v2 09/22] drm/msm/dpu: remove dpu_hw_pipe_cdp_cfg " Dmitry Baryshkov
2021-07-05 1:21 ` [PATCH v2 10/22] drm/msm/dpu: don't cache pipe->cap->features in dpu_plane Dmitry Baryshkov
2021-07-05 1:21 ` [PATCH v2 11/22] drm/msm/dpu: don't cache pipe->cap->sblk " Dmitry Baryshkov
2021-07-05 1:21 ` [PATCH v2 12/22] drm/msm/dpu: rip out debugfs support from dpu_plane Dmitry Baryshkov
2021-07-05 1:21 ` [PATCH v2 13/22] drm/msm/dpu: drop src_split and multirect check from dpu_crtc_atomic_check Dmitry Baryshkov
2021-07-05 1:21 ` [PATCH v2 14/22] drm/msm/dpu: add list of supported formats to the DPU caps Dmitry Baryshkov
2021-11-09 20:05 ` [Freedreno] " abhinavk
2021-07-05 1:21 ` [PATCH v2 15/22] drm/msm/dpu: simplify DPU_SSPP features checks Dmitry Baryshkov
2021-11-09 20:06 ` [Freedreno] " abhinavk
2021-07-05 1:21 ` [PATCH v2 16/22] drm/msm/dpu: do not limit the zpos property Dmitry Baryshkov
2021-11-09 20:15 ` [Freedreno] " abhinavk
2021-11-09 20:21 ` Dmitry Baryshkov
2021-11-10 1:35 ` abhinavk
2021-11-10 1:58 ` Dmitry Baryshkov
2021-07-05 1:21 ` [PATCH v2 17/22] drm/msm/dpu: add support for SSPP allocation to RM Dmitry Baryshkov
2021-11-10 0:30 ` [Freedreno] " abhinavk
2021-07-05 1:21 ` [PATCH v2 18/22] drm/msm/dpu: move pipe_hw to dpu_plane_state Dmitry Baryshkov
2021-07-05 1:21 ` [PATCH v2 19/22] drm/msm/dpu: add support for virtualized planes Dmitry Baryshkov
2021-07-05 1:21 ` [PATCH v2 20/22] drm/msm/dpu: fix smart dma support Dmitry Baryshkov
2021-11-10 2:06 ` [Freedreno] " abhinavk
2021-07-05 1:21 ` [PATCH v2 21/22] drm/msm/dpu: fix CDP setup to account for multirect index Dmitry Baryshkov
2021-11-10 2:12 ` abhinavk [this message]
2021-07-05 1:21 ` [PATCH v2 22/22] drm/msm/dpu: add multirect support Dmitry Baryshkov
2021-11-10 2:22 ` [Freedreno] " abhinavk
2021-09-30 2:19 ` [Freedreno] [PATCH v2 00/22] drm/msm/dpu: switch dpu_plane to be virtual abhinavk
2021-09-30 10:56 ` Dmitry Baryshkov
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