From: Rob Herring <robh@kernel.org>
To: Jordan Crouse <jcrouse@codeaurora.org>
Cc: linux-arm-msm@vger.kernel.org, smasetty@codeaurora.org,
John Stultz <john.stultz@linaro.org>, Sean Paul <sean@poorly.run>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
dri-devel@lists.freedesktop.org, Rob Clark <robdclark@gmail.com>,
David Airlie <airlied@linux.ie>,
Mark Rutland <mark.rutland@arm.com>,
freedreno@lists.freedesktop.org, Daniel Vetter <daniel@ffwll.ch>
Subject: Re: [PATCH v2 1/4] dt-bindings: display: msm: Convert GMU bindings to YAML
Date: Wed, 26 Feb 2020 10:33:42 -0600 [thread overview]
Message-ID: <20200226163342.GA26694@bogus> (raw)
In-Reply-To: <1582223216-23459-2-git-send-email-jcrouse@codeaurora.org>
On Thu, Feb 20, 2020 at 11:26:53AM -0700, Jordan Crouse wrote:
> Convert display/msm/gmu.txt to display/msm/gmu.yaml and remove the old
> text bindings.
>
> Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
> ---
>
> .../devicetree/bindings/display/msm/gmu.txt | 116 ------------------
> .../devicetree/bindings/display/msm/gmu.yaml | 130 +++++++++++++++++++++
> 2 files changed, 130 insertions(+), 116 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/display/msm/gmu.txt
> create mode 100644 Documentation/devicetree/bindings/display/msm/gmu.yaml
> diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml b/Documentation/devicetree/bindings/display/msm/gmu.yaml
> new file mode 100644
> index 0000000..776ff92
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/msm/gmu.yaml
> @@ -0,0 +1,130 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +# Copyright 2019-2020, The Linux Foundation, All Rights Reserved
> +%YAML 1.2
> +---
> +
> +$id: "http://devicetree.org/schemas/display/msm/gmu.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Devicetree bindings for the GMU attached to certain Adreno GPUs
> +
> +maintainers:
> + - Rob Clark <robdclark@gmail.com>
> +
> +description: |
> + These bindings describe the Graphics Management Unit (GMU) that is attached
> + to members of the Adreno A6xx GPU family. The GMU provides on-device power
> + management and support to improve power efficiency and reduce the load on
> + the CPU.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - qcom,adreno-gmu-630.2
> + - const: qcom,adreno-gmu
> +
> + reg:
> + items:
> + - description: Core GMU registers
> + - description: GMU PDC registers
> + - description: GMU PDC sequence registers
> +
> + reg-names:
> + items:
> + - const: gmu
> + - const: gmu_pdc
> + - const: gmu_pdc_seq
> +
> + clocks:
> + items:
> + - description: GMU clock
> + - description: GPU CX clock
> + - description: GPU AXI clock
> + - description: GPU MEMNOC clock
> +
> + clock-names:
> + items:
> + - const: gmu
> + - const: cxo
> + - const: axi
> + - const: memnoc
> +
> + interrupts:
> + items:
> + - description: GMU HFI interrupt
> + - description: GMU interrupt
> +
> +
> + interrupt-names:
> + items:
> + - const: hfi
> + - const: gmu
> +
> + power-domains:
> + items:
> + - description: CX power domain
> + - description: GX power domain
> +
> + power-domain-names:
> + items:
> + - const: cx
> + - const: gx
> +
> + iommus:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
Already has a type. Just need to define how many entries (maxItems).
> + description:
> + Phandle to a IOMMU device and stream ID. Refer to ../../iommu/iommu.txt
> + for more information.
Drop. That's all iommus entries.
> +
> + operating-points-v2:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description:
> + Phandle to the OPP table for the available GMU frequencies. Refer to
> + ../../opp/opp.txt for more information.
Just 'true' is enough here.
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - clocks
> + - clock-names
> + - interrupts
> + - interrupt-names
> + - power-domains
> + - power-domain-names
> + - iommus
> + - operating-points-v2
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
> + #include <dt-bindings/clock/qcom,gcc-sdm845.h>
> + #include <dt-bindings/interrupt-controller/irq.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + gmu: gmu@506a000 {
> + compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
> +
> + reg = <0x506a000 0x30000>,
> + <0xb280000 0x10000>,
> + <0xb480000 0x10000>;
> + reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
> +
> + clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
> + <&gpucc GPU_CC_CXO_CLK>,
> + <&gcc GCC_DDRSS_GPU_AXI_CLK>,
> + <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
> + clock-names = "gmu", "cxo", "axi", "memnoc";
> +
> + interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "hfi", "gmu";
> +
> + power-domains = <&gpucc GPU_CX_GDSC>,
> + <&gpucc GPU_GX_GDSC>;
> + power-domain-names = "cx", "gx";
> +
> + iommus = <&adreno_smmu 5>;
> + operating-points-v2 = <&gmu_opp_table>;
> + };
> --
> 2.7.4
>
next prev parent reply other threads:[~2020-02-26 16:33 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-20 18:26 [PATCH v2 0/4] msm/gpu/a6xx: use the DMA-API for GMU memory allocations Jordan Crouse
2020-02-20 18:26 ` [PATCH v2 1/4] dt-bindings: display: msm: Convert GMU bindings to YAML Jordan Crouse
2020-02-26 16:33 ` Rob Herring [this message]
2020-02-20 18:26 ` [PATCH v2 2/4] dt-bindings: display: msm: Add required dma-range property Jordan Crouse
2020-02-25 18:55 ` Rob Herring
2020-02-20 18:26 ` [PATCH v2 3/4] arm64: dts: sdm845: Set the virtual address range for GMU allocations Jordan Crouse
2020-02-20 18:26 ` [PATCH v2 4/4] drm/msm/a6xx: Use the DMA API for GMU memory objects Jordan Crouse
2020-02-25 23:54 ` John Stultz
2020-02-26 0:59 ` Rob Clark
2020-02-21 0:19 ` [PATCH v2 0/4] msm/gpu/a6xx: use the DMA-API for GMU memory allocations John Stultz
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