From: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
To: linux-arm-msm@vger.kernel.org
Cc: konrad.dybcio@somainline.org, marijn.suijten@somainline.org,
martin.botka@somainline.org, phone-devel@vger.kernel.org,
robdclark@gmail.com, sean@poorly.run,
dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org,
linux-kernel@vger.kernel.org,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@somainline.org>
Subject: [PATCH v2 1/7] drm/msm/dpu: Fix VBIF_XINL_QOS_LVL_REMAP_000 register offset
Date: Tue, 12 Jan 2021 20:26:26 +0100 [thread overview]
Message-ID: <20210112192632.502897-2-angelogioacchino.delregno@somainline.org> (raw)
In-Reply-To: <20210112192632.502897-1-angelogioacchino.delregno@somainline.org>
On DPUs prior to version 4 the VBIF_XINL_QOS_LVL_REMAP_000 register
is at 0x570 offset from vbif base instead of 0x590, due to the
VBIF_XINL_QOS_RP_REMAP_000 having less instances (less possible XINs).
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c
index cf867f3f7c36..b757054e1c23 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c
@@ -30,7 +30,7 @@
#define VBIF_XIN_HALT_CTRL0 0x0200
#define VBIF_XIN_HALT_CTRL1 0x0204
#define VBIF_XINL_QOS_RP_REMAP_000 0x0550
-#define VBIF_XINL_QOS_LVL_REMAP_000 0x0590
+#define VBIF_XINL_QOS_LVL_REMAP_000(v) (v < DPU_HW_VER_400 ? 0x570 : 0x0590)
static void dpu_hw_clear_errors(struct dpu_hw_vbif *vbif,
u32 *pnd_errors, u32 *src_errors)
@@ -156,18 +156,19 @@ static void dpu_hw_set_qos_remap(struct dpu_hw_vbif *vbif,
u32 xin_id, u32 level, u32 remap_level)
{
struct dpu_hw_blk_reg_map *c;
- u32 reg_val, reg_val_lvl, mask, reg_high, reg_shift;
+ u32 reg_lvl, reg_val, reg_val_lvl, mask, reg_high, reg_shift;
if (!vbif)
return;
c = &vbif->hw;
+ reg_lvl = VBIF_XINL_QOS_LVL_REMAP_000(c->hwversion);
reg_high = ((xin_id & 0x8) >> 3) * 4 + (level * 8);
reg_shift = (xin_id & 0x7) * 4;
reg_val = DPU_REG_READ(c, VBIF_XINL_QOS_RP_REMAP_000 + reg_high);
- reg_val_lvl = DPU_REG_READ(c, VBIF_XINL_QOS_LVL_REMAP_000 + reg_high);
+ reg_val_lvl = DPU_REG_READ(c, reg_lvl + reg_high);
mask = 0x7 << reg_shift;
@@ -178,7 +179,7 @@ static void dpu_hw_set_qos_remap(struct dpu_hw_vbif *vbif,
reg_val_lvl |= (remap_level << reg_shift) & mask;
DPU_REG_WRITE(c, VBIF_XINL_QOS_RP_REMAP_000 + reg_high, reg_val);
- DPU_REG_WRITE(c, VBIF_XINL_QOS_LVL_REMAP_000 + reg_high, reg_val_lvl);
+ DPU_REG_WRITE(c, reg_lvl + reg_high, reg_val_lvl);
}
static void dpu_hw_set_write_gather_en(struct dpu_hw_vbif *vbif, u32 xin_id)
--
2.29.2
next prev parent reply other threads:[~2021-01-12 19:28 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-12 19:26 [PATCH v2 0/7] Qualcomm DRM DPU fixes AngeloGioacchino Del Regno
2021-01-12 19:26 ` AngeloGioacchino Del Regno [this message]
2021-01-12 19:26 ` [PATCH v2 2/7] drm/msm/dpu: Move DPU_SSPP_QOS_8LVL bit to SDM845 and SC7180 masks AngeloGioacchino Del Regno
2021-01-12 19:26 ` [PATCH v2 3/7] drm/msm/dpu: Add prog_fetch_lines_worst_case to INTF_BLK macro AngeloGioacchino Del Regno
2021-01-12 19:26 ` [PATCH v2 4/7] drm/msm/dpu: Allow specifying features and sblk in DSPP_BLK macro AngeloGioacchino Del Regno
2021-01-12 19:26 ` [PATCH v2 5/7] drm/msm/dpu: Disable autorefresh in command mode AngeloGioacchino Del Regno
2021-01-12 19:26 ` [PATCH v2 6/7] drm/msm/dpu: Correctly configure vsync tearcheck for " AngeloGioacchino Del Regno
2021-01-12 19:26 ` [PATCH v2 7/7] drm/msm/dpu: Remove unused call in wait_for_commit_done AngeloGioacchino Del Regno
2021-03-01 19:59 ` [PATCH v2 0/7] Qualcomm DRM DPU fixes patchwork-bot+linux-arm-msm
2021-05-15 23:04 ` Dmitry Baryshkov
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