[PATCH v2 2/3] arm64: dts: qcom: sm8250: Add SDHCI2 pinctrl

[Konrad Dybcio <konrad.dybcio@somainline.org>]

Add required pins for SDHCI2, so that the interface can work reliably.
The configuration comes from a MTP board, which conveniently means it's
going to be correct for the vast majority of phones (and other devices).

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
---
Changes since v1:
- Separate this into its own patch

 arch/arm64/boot/dts/qcom/sm8250.dtsi | 32 ++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index fc1049c2bb11..fe858abbff5d 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -8,6 +8,7 @@
 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
 #include <dt-bindings/clock/qcom,gpucc-sm8250.h>
 #include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interconnect/qcom,osm-l3.h>
 #include <dt-bindings/interconnect/qcom,sm8250.h>
 #include <dt-bindings/mailbox/qcom-ipcc.h>
@@ -2157,6 +2158,10 @@ sdhc_2: sdhci@8804000 {
 			power-domains = <&rpmhpd SM8250_CX>;
 			operating-points-v2 = <&sdhc2_opp_table>;
 
+			cd-gpios = <&tlmm 77 GPIO_ACTIVE_HIGH>;
+			pinctrl-0 = <&sdc2_default_state &sdc2_card_det_n>;
+			pinctrl-names = "default";
+
 			status = "disabled";
 
 			sdhc2_opp_table: sdhc2-opp-table {
@@ -3401,6 +3406,33 @@ ws {
 					output-high;
 				};
 			};
+
+			sdc2_default_state: sdc2-default {
+				clk {
+					pins = "sdc2_clk";
+					drive-strength = <16>;
+					bias-disable;
+				};
+
+				cmd {
+					pins = "sdc2_cmd";
+					drive-strength = <16>;
+					bias-pull-up;
+				};
+
+				data {
+					pins = "sdc2_data";
+					drive-strength = <16>;
+					bias-pull-up;
+				};
+			};
+
+			sdc2_card_det_n: sd-card-det-n {
+				pins = "gpio77";
+				function = "gpio";
+				bias-pull-up;
+				drive-strength = <2>;
+			};
 		};
 
 		apps_smmu: iommu@15000000 {
-- 
2.32.0