From: Thara Gopinath <thara.gopinath@linaro.org>
To: agross@kernel.org, bjorn.andersson@linaro.org,
rui.zhang@intel.com, daniel.lezcano@linaro.org,
viresh.kumar@linaro.org, rjw@rjwysocki.net, robh+dt@kernel.org
Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
Subject: [Patch v2 4/5] arm64: boot: dts: qcom: sdm45: Add support for LMh node
Date: Thu, 24 Jun 2021 07:58:12 -0400 [thread overview]
Message-ID: <20210624115813.3613290-5-thara.gopinath@linaro.org> (raw)
In-Reply-To: <20210624115813.3613290-1-thara.gopinath@linaro.org>
Add LMh nodes for cpu cluster0 and cpu cluster1. Also add interrupt
support in cpufreq node to capture the LMh interrupt and let the scheduler
know of the max frequency throttling.
Signed-off-by: Thara Gopinath <thara.gopinath@linaro.org>
---
v1->v2:
- Dropped dt property qcom,support-lmh as per Bjorn's review comments.
- Changed lmh compatible from generic to platform specific.
- Introduced properties specifying arm, low and high temp thresholds for LMh
as per Daniel's suggestion.
arch/arm64/boot/dts/qcom/sdm845.dtsi | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 0a86fe71a66d..202fec09becd 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -3646,6 +3646,30 @@ swm: swm@c85 {
};
};
+ lmh_cluster1: lmh@17d70800 {
+ compatible = "qcom,sdm845-lmh";
+ reg = <0 0x17d70800 0 0x401>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,lmh-cpu-id = <0x4>;
+ qcom,lmh-temperature-arm = <65000>;
+ qcom,lmh-temperature-low = <74500>;
+ qcom,lmh-temperature-high = <75000>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ lmh_cluster0: lmh@17d78800 {
+ compatible = "qcom,sdm845-lmh";
+ reg = <0 0x17d78800 0 0x401>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,lmh-cpu-id = <0x0>;
+ qcom,lmh-temperature-arm = <65000>;
+ qcom,lmh-temperature-low = <74500>;
+ qcom,lmh-temperature-high = <75000>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
sound: sound {
};
@@ -4911,6 +4935,8 @@ cpufreq_hw: cpufreq@17d43000 {
reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;
reg-names = "freq-domain0", "freq-domain1";
+ interrupts-extended = <&lmh_cluster0 0>, <&lmh_cluster1 0>;
+
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
clock-names = "xo", "alternate";
--
2.25.1
next prev parent reply other threads:[~2021-06-24 11:58 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-24 11:58 [Patch v2 0/5] Introduce LMh driver for Qualcomm SoCs Thara Gopinath
2021-06-24 11:58 ` [Patch v2 1/5] firmware: qcom_scm: Introduce SCM calls to access LMh Thara Gopinath
2021-06-24 17:48 ` Matthias Kaehlcke
2021-06-25 15:45 ` Thara Gopinath
2021-06-24 11:58 ` [Patch v2 2/5] thermal: qcom: Add support for LMh driver Thara Gopinath
2021-06-24 17:24 ` Matthias Kaehlcke
2021-06-30 3:06 ` Thara Gopinath
2021-06-24 11:58 ` [Patch v2 3/5] cpufreq: qcom-cpufreq-hw: Add dcvs interrupt support Thara Gopinath
2021-06-29 2:35 ` Viresh Kumar
2021-06-30 2:25 ` Thara Gopinath
2021-06-30 3:53 ` Viresh Kumar
2021-06-29 2:50 ` Taniya Das
2021-06-30 2:27 ` Thara Gopinath
2021-06-24 11:58 ` Thara Gopinath [this message]
2021-06-24 11:58 ` [Patch v2 5/5] arm64: boot: dts: qcom: sdm845: Remove passive trip points for thermal zones 0-7 Thara Gopinath
2021-06-24 16:51 ` Matthias Kaehlcke
2021-06-25 15:44 ` Thara Gopinath
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