From: Rob Herring <robh@kernel.org>
To: Lina Iyer <ilina@codeaurora.org>
Cc: swboyd@chromium.org, evgreen@chromium.org, marc.zyngier@arm.com,
linus.walleij@linaro.org, linux-kernel@vger.kernel.org,
linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org,
mkshah@codeaurora.org, linux-gpio@vger.kernel.org,
rnayak@codeaurora.org, devicetree@vger.kernel.org
Subject: Re: [PATCH RFC 05/14] dt-bindings/interrupt-controller: pdc: add SPI config register
Date: Mon, 02 Sep 2019 14:38:57 +0100 [thread overview]
Message-ID: <5d6d1b72.1c69fb81.ee88.efcf@mx.google.com> (raw)
In-Reply-To: <20190829181203.2660-6-ilina@codeaurora.org>
On Thu, Aug 29, 2019 at 12:11:54PM -0600, Lina Iyer wrote:
> In addition to configuring the PDC, additional registers that interface
> the GIC have to be configured to match the GPIO type. The registers on
> some QCOM SoCs are access restricted, while on other SoCs are not. They
> SoCs with access restriction to these SPI registers need to be written
Took me a minute to figure out this is GIC SPI interrupts, not SPI bus.
> from the firmware using the SCM interface. Add a flag to indicate if the
> register is to be written using SCM interface.
>
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Lina Iyer <ilina@codeaurora.org>
> ---
> .../bindings/interrupt-controller/qcom,pdc.txt | 9 ++++++++-
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt
> index 8e0797cb1487..852fcba98ea6 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt
> +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt
> @@ -50,15 +50,22 @@ Properties:
> The second element is the GIC hwirq number for the PDC port.
> The third element is the number of interrupts in sequence.
>
> +- qcom,scm-spi-cfg:
> + Usage: optional
> + Value type: <bool>
> + Definition: Specifies if the SPI configuration registers have to be
> + written from the firmware.
> +
> Example:
>
> pdc: interrupt-controller@b220000 {
> compatible = "qcom,sdm845-pdc";
> - reg = <0xb220000 0x30000>;
> + reg = <0xb220000 0x30000>, <0x179900f0 0x60>;
There needs to be a description for reg updated. These aren't GIC
registers are they? Because those go in the GIC node.
> qcom,pdc-ranges = <0 512 94>, <94 641 15>, <115 662 7>;
> #interrupt-cells = <2>;
> interrupt-parent = <&intc>;
> interrupt-controller;
> + qcom,scm-spi-cfg;
> };
>
> DT binding of a device that wants to use the GIC SPI 514 as a wakeup
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
next prev parent reply other threads:[~2019-09-02 13:40 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-29 18:11 [PATCH RFC 00/14] qcom: support wakeup capable GPIOs Lina Iyer
2019-08-29 18:11 ` [PATCH RFC 01/14] irqdomain: add bus token DOMAIN_BUS_WAKEUP Lina Iyer
2019-08-29 18:11 ` [PATCH RFC 02/14] drivers: irqchip: pdc: Do not toggle IRQ_ENABLE during mask/unmask Lina Iyer
2019-09-06 0:39 ` Stephen Boyd
2019-09-11 16:15 ` Lina Iyer
2019-09-20 22:22 ` Stephen Boyd
2019-09-20 22:31 ` Lina Iyer
2019-08-29 18:11 ` [PATCH RFC 03/14] drivers: irqchip: add PDC irqdomain for wakeup capable GPIOs Lina Iyer
2019-08-30 14:50 ` Marc Zyngier
2019-08-30 15:58 ` Lina Iyer
2019-09-02 8:21 ` Marc Zyngier
2019-09-03 22:51 ` Stephen Boyd
2019-08-29 18:11 ` [PATCH RFC 04/14] of: irq: document properties for wakeup interrupt parent Lina Iyer
2019-09-02 13:38 ` Rob Herring
2019-08-29 18:11 ` [PATCH RFC 05/14] dt-bindings/interrupt-controller: pdc: add SPI config register Lina Iyer
2019-09-02 13:38 ` Rob Herring [this message]
2019-09-02 13:53 ` Marc Zyngier
2019-09-03 17:07 ` Lina Iyer
2019-09-06 0:03 ` Stephen Boyd
2019-09-13 19:53 ` Lina Iyer
2019-09-17 21:50 ` Lina Iyer
2019-09-20 22:20 ` Stephen Boyd
2019-09-23 6:11 ` Sibi Sankar
[not found] ` <CACRpkdaReFzjb_hcDbQwqMX+whzscLpeZpJPHKqOo+9tANzemA@mail.gmail.com>
2019-09-11 15:19 ` Lina Iyer
2019-08-29 18:11 ` [PATCH RFC 06/14] drivers: irqchip: pdc: additionally set type in SPI config registers Lina Iyer
2019-09-06 0:22 ` Stephen Boyd
2019-08-29 18:11 ` [PATCH RFC 07/14] genirq: Introduce irq_chip_get/set_parent_state calls Lina Iyer
2019-09-06 0:35 ` Stephen Boyd
2019-08-29 18:11 ` [PATCH RFC 08/14] drivers: irqchip: pdc: Add irqchip set/get state calls Lina Iyer
2019-09-06 0:09 ` Stephen Boyd
2019-08-29 18:11 ` [PATCH RFC 09/14] drivers: pinctrl: msm: fix use of deprecated gpiolib APIs Lina Iyer
2019-09-06 0:11 ` Stephen Boyd
2019-09-11 10:19 ` Linus Walleij
2019-09-11 16:16 ` Lina Iyer
2019-08-29 18:11 ` [PATCH RFC 10/14] drivers: pinctrl: msm: setup GPIO chip in hierarchy Lina Iyer
2019-08-29 18:12 ` [PATCH RFC 11/14] drivers: pinctrl: sdm845: add PDC wakeup interrupt map for GPIOs Lina Iyer
2019-09-06 0:24 ` Stephen Boyd
2019-08-29 18:12 ` [PATCH RFC 12/14] arm64: dts: qcom: add PDC interrupt controller for SDM845 Lina Iyer
2019-09-09 11:26 ` Maulik Shah
2019-08-29 18:12 ` [PATCH RFC 13/14] arm64: dts: qcom: setup PDC as the wakeup parent for TLMM on SDM845 Lina Iyer
2019-08-29 18:12 ` [PATCH RFC 14/14] arm64: defconfig: enable PDC interrupt controller for Qualcomm SDM845 Lina Iyer
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