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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id p9sm514199otl.64.2021.05.31.08.58.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 May 2021 08:58:08 -0700 (PDT) Date: Mon, 31 May 2021 10:58:06 -0500 From: Bjorn Andersson To: Jonathan McDowell Cc: Andy Gross , Rob Herring , Ansuel Smith , Vinod Koul , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 3/5] ARM: dts: qcom: Add USB port definitions to ipq806x Message-ID: References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Thu 20 May 12:30 CDT 2021, Jonathan McDowell wrote: > Signed-off-by: Jonathan McDowell > --- > arch/arm/boot/dts/qcom-ipq8064.dtsi | 88 +++++++++++++++++++++++++++++ > 1 file changed, 88 insertions(+) > > diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi > index 9628092217cb..c66859abdfd5 100644 > --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi > +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi > @@ -1026,6 +1026,94 @@ > status = "disabled"; > }; > > + hs_phy_0: hs_phy_0 { The node name should be some generic-thing@unit-address, so I fixed up all your phys as "phy@100f8800" while applying your patches. Thank you, Bjorn > + compatible = "qcom,ipq806x-usb-phy-hs"; > + reg = <0x100f8800 0x30>; > + clocks = <&gcc USB30_0_UTMI_CLK>; > + clock-names = "ref"; > + #phy-cells = <0>; > + > + status = "disabled"; > + }; > + > + ss_phy_0: ss_phy_0 { > + compatible = "qcom,ipq806x-usb-phy-ss"; > + reg = <0x100f8830 0x30>; > + clocks = <&gcc USB30_0_MASTER_CLK>; > + clock-names = "ref"; > + #phy-cells = <0>; > + > + status = "disabled"; > + }; > + > + usb3_0: usb3@100f8800 { > + compatible = "qcom,dwc3", "syscon"; > + #address-cells = <1>; > + #size-cells = <1>; > + reg = <0x100f8800 0x8000>; > + clocks = <&gcc USB30_0_MASTER_CLK>; > + clock-names = "core"; > + > + ranges; > + > + resets = <&gcc USB30_0_MASTER_RESET>; > + reset-names = "master"; > + > + status = "disabled"; > + > + dwc3_0: dwc3@10000000 { > + compatible = "snps,dwc3"; > + reg = <0x10000000 0xcd00>; > + interrupts = ; > + phys = <&hs_phy_0>, <&ss_phy_0>; > + phy-names = "usb2-phy", "usb3-phy"; > + dr_mode = "host"; > + snps,dis_u3_susphy_quirk; > + }; > + }; > + > + hs_phy_1: hs_phy_1 { > + compatible = "qcom,ipq806x-usb-phy-hs"; > + reg = <0x110f8800 0x30>; > + clocks = <&gcc USB30_1_UTMI_CLK>; > + clock-names = "ref"; > + #phy-cells = <0>; > + }; > + > + ss_phy_1: ss_phy_1 { > + compatible = "qcom,ipq806x-usb-phy-ss"; > + reg = <0x110f8830 0x30>; > + clocks = <&gcc USB30_1_MASTER_CLK>; > + clock-names = "ref"; > + #phy-cells = <0>; > + }; > + > + usb3_1: usb3@110f8800 { > + compatible = "qcom,dwc3", "syscon"; > + #address-cells = <1>; > + #size-cells = <1>; > + reg = <0x110f8800 0x8000>; > + clocks = <&gcc USB30_1_MASTER_CLK>; > + clock-names = "core"; > + > + ranges; > + > + resets = <&gcc USB30_1_MASTER_RESET>; > + reset-names = "master"; > + > + status = "disabled"; > + > + dwc3_1: dwc3@11000000 { > + compatible = "snps,dwc3"; > + reg = <0x11000000 0xcd00>; > + interrupts = ; > + phys = <&hs_phy_1>, <&ss_phy_1>; > + phy-names = "usb2-phy", "usb3-phy"; > + dr_mode = "host"; > + snps,dis_u3_susphy_quirk; > + }; > + }; > + > vsdcc_fixed: vsdcc-regulator { > compatible = "regulator-fixed"; > regulator-name = "SDCC Power"; > -- > 2.20.1 >