From: Bjorn Andersson <bjorn.andersson@linaro.org>
To: Roja Rani Yarubandi <rojay@codeaurora.org>
Cc: agross@kernel.org, robh+dt@kernel.org,
linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
Rajendra Nayak <rnayak@codeaurora.org>,
saiprakash.ranjan@codeaurora.org, msavaliy@qti.qualcomm.com
Subject: Re: [PATCH V3 2/3] arm64: dts: sc7280: Add QUPv3 wrapper_0 nodes
Date: Sat, 5 Jun 2021 22:49:54 -0500 [thread overview]
Message-ID: <YLxF4rGFDrFXQRDi@builder.lan> (raw)
In-Reply-To: <20210604135439.19119-3-rojay@codeaurora.org>
On Fri 04 Jun 08:54 CDT 2021, Roja Rani Yarubandi wrote:
> Add QUPv3 wrapper_0 DT nodes for SC7280 SoC.
>
> Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
> ---
> Changes in V3:
> - Broken the huge V2 patch into 3 smaller patches.
> 1. QSPI DT nodes
> 2. QUP wrapper_0 DT nodes
> 3. QUP wrapper_1 DT nodes
>
> Changes in V2:
> - As per Doug's comments removed pinmux/pinconf subnodes.
> - As per Doug's comments split of SPI, UART nodes has been done.
> - Moved QSPI node before aps_smmu as per the order.
>
> arch/arm64/boot/dts/qcom/sc7280-idp.dts | 97 ++-
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 750 +++++++++++++++++++++++-
> 2 files changed, 835 insertions(+), 12 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> index d0edffc15736..f57458dbe763 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> @@ -292,6 +292,16 @@ &uart5 {
> status = "okay";
> };
>
> +&uart7 {
> + status = "okay";
> +
> + /delete-property/interrupts;
> + interrupts-extended = <&intc GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>,
> + <&tlmm 31 IRQ_TYPE_EDGE_FALLING>;
> + pinctrl-names = "default", "sleep";
> + pinctrl-1 = <&qup_uart7_sleep_cts>, <&qup_uart7_sleep_rts>, <&qup_uart7_sleep_tx>, <&qup_uart7_sleep_rx>;
> +};
> +
> /* PINCTRL - additions to nodes defined in sc7280.dtsi */
>
> &qspi_cs0 {
> @@ -307,16 +317,87 @@ &qspi_data01 {
> bias-pull-up;
> };
>
> -&qup_uart5_default {
> - tx {
> - pins = "gpio46";
Commit message says "add stuff", but somehow uart5 is no longer
gpio46/47 and these gpios are no longer specified.
Can you roll this in a way where the giant patch actually _only_ adds
a whole bunch of stuff?
> - drive-strength = <2>;
> - bias-disable;
> +&qup_uart5_tx {
> + drive-strength = <2>;
> + bias-disable;
> +};
> +
Regards,
Bjorn
next prev parent reply other threads:[~2021-06-06 3:51 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-04 13:54 [PATCH V3 0/3] Add QSPI and QUPv3 DT nodes for SC7280 SoC Roja Rani Yarubandi
2021-06-04 13:54 ` [PATCH V3 1/3] arm64: dts: sc7280: Add QSPI node Roja Rani Yarubandi
2021-06-04 21:45 ` Stephen Boyd
2021-06-08 8:05 ` rojay
2021-06-06 3:55 ` Bjorn Andersson
2021-06-08 8:07 ` rojay
2021-07-06 9:19 ` rojay
2021-07-09 0:56 ` Stephen Boyd
2021-07-14 7:47 ` rojay
2021-07-19 20:08 ` Bjorn Andersson
2021-09-09 4:43 ` rajpat
2021-06-04 13:54 ` [PATCH V3 2/3] arm64: dts: sc7280: Add QUPv3 wrapper_0 nodes Roja Rani Yarubandi
2021-06-06 3:49 ` Bjorn Andersson [this message]
2021-06-08 8:16 ` rojay
2021-06-04 13:54 ` [PATCH V3 3/3] arm64: dts: sc7280: Add QUPv3 wrapper_1 nodes Roja Rani Yarubandi
2021-06-06 3:53 ` Bjorn Andersson
2021-06-08 8:10 ` rojay
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