From: Matthias Kaehlcke <mka@chromium.org>
To: rajpat@codeaurora.org
Cc: Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
swboyd@chromium.org, linux-arm-msm@vger.kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
rnayak@codeaurora.org, saiprakash.ranjan@codeaurora.org,
msavaliy@qti.qualcomm.com, skakit@codeaurora.org
Subject: Re: [PATCH V5 3/7] arm64: dts: sc7280: Add QUPv3 wrapper_0 nodes
Date: Thu, 26 Aug 2021 12:51:34 -0700 [thread overview]
Message-ID: <YSfwxuX22Ix4fqX2@google.com> (raw)
In-Reply-To: <114d7419b0a85fcacf775cc34f279f0e@codeaurora.org>
On Thu, Aug 26, 2021 at 06:37:02PM +0530, rajpat@codeaurora.org wrote:
> On 2021-08-12 19:44, Matthias Kaehlcke wrote:
> > On Thu, Aug 12, 2021 at 01:11:14PM +0530, Rajesh Patil wrote:
> > > From: Roja Rani Yarubandi <rojay@codeaurora.org>
> > >
> > > Add QUPv3 wrapper_0 DT nodes for SC7280 SoC.
> > >
> > > Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
> > > Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
> > > ---
> > > arch/arm64/boot/dts/qcom/sc7280.dtsi | 720
> > > +++++++++++++++++++++++++++++++++++
> > > 1 file changed, 720 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > > b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > > index f8dd5ff..e461395 100644
> > > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > >
> > > ...
> > >
> > > + spi0: spi@980000 {
> > > + compatible = "qcom,geni-spi";
> > > + reg = <0 0x00980000 0 0x4000>;
> > > + clock-names = "se";
> > > + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
> > > + pinctrl-names = "default";
> > > + pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>,
> > > <&qup_spi0_cs_gpio>;
> >
> > What is the story behind 'qup_spiN_cs' and 'qup_spiN_cs_gpio'? Both
> > configure
> > the CS pin with a different function:
> >
>
> As per discussion here [1], we have split like this.
>
> [1] https://lore.kernel.org/patchwork/patch/1393353/#1591826
IIUC that's only about having separate configs for each pin, instead of
groups like 'qup-spi0-default'. What you are doing above with 'qup_spi0_cs'
and 'qup_spi0_cs_gpio' is to configure the same pin (GPIO 3) both as SPI
chip select and as GPIO. Which one is it?
I imagine we want to have both pinctrl definitions to allow a board to
configure the pin either as SPI CS or GPIO. However it should be only one
of the two at a time, and the SoC .dtsi should provide a reasonable
default, which probably is SPI CS.
Maybe I'm missing something, if so please provide details on why it is
necessary to have this config.
next prev parent reply other threads:[~2021-08-26 19:51 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-12 7:41 [PATCH V5 0/7] Add QSPI and QUPv3 DT nodes for SC7280 SoC Rajesh Patil
2021-08-12 7:41 ` [PATCH V5 1/7] arm64: dts: sc7280: Add QSPI node Rajesh Patil
2021-08-12 13:09 ` Matthias Kaehlcke
2021-08-26 12:59 ` rajpat
2021-09-03 15:46 ` Matthias Kaehlcke
2021-08-12 7:41 ` [PATCH V5 2/7] arm64: dts: sc7280: Configure SPI-NOR FLASH for sc7280-idp Rajesh Patil
2021-08-12 13:15 ` Matthias Kaehlcke
2021-08-23 11:44 ` rajpat
2021-08-12 7:41 ` [PATCH V5 3/7] arm64: dts: sc7280: Add QUPv3 wrapper_0 nodes Rajesh Patil
2021-08-12 14:14 ` Matthias Kaehlcke
2021-08-12 16:22 ` Matthias Kaehlcke
2021-08-26 13:07 ` rajpat
2021-08-26 19:51 ` Matthias Kaehlcke [this message]
2021-09-01 7:06 ` rajpat
2021-08-19 0:04 ` Doug Anderson
2021-08-26 12:53 ` rajpat
2021-08-12 7:41 ` [PATCH V5 4/7] arm64: dts: sc7280: Update QUPv3 UART5 DT node Rajesh Patil
2021-08-12 15:46 ` Matthias Kaehlcke
2021-08-12 7:41 ` [PATCH V5 5/7] arm64: dts: sc7280: Configure debug uart for sc7280-idp Rajesh Patil
2021-08-12 16:05 ` Matthias Kaehlcke
2021-08-26 13:07 ` rajpat
2021-08-12 7:41 ` [PATCH V5 6/7] arm64: dts: sc7280: Configure uart7 to support bluetooth on sc7280-idp Rajesh Patil
2021-08-12 19:22 ` Matthias Kaehlcke
2021-08-12 7:41 ` [PATCH V5 7/7] arm64: dts: sc7280: Add QUPv3 wrapper_1 nodes Rajesh Patil
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