From: Jonathan Marek <jonathan@marek.ca>
To: Vinod Koul <vkoul@kernel.org>
Cc: linux-arm-msm@vger.kernel.org, robert.foss@linaro.org,
andrey.konovalov@linaro.org, Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
"open list:COMMON CLK FRAMEWORK" <linux-clk@vger.kernel.org>,
open list <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 1/3] clk: qcom: clk-alpha-pll: add support for zonda pll
Date: Tue, 18 May 2021 09:06:23 -0400 [thread overview]
Message-ID: <abc662f3-8c36-862d-4d50-3628d3a02ee2@marek.ca> (raw)
In-Reply-To: <YKOltGEDEY1WXQN6@vkoul-mobl.Dlink>
On 5/18/21 7:32 AM, Vinod Koul wrote:
> On 13-05-21, 13:52, Jonathan Marek wrote:
...
>> +/* ZONDA PLL specific */
>> +#define ZONDA_PLL_OUT_MASK 0xf
>> +#define ZONDA_STAY_IN_CFA BIT(16)
>> +#define ZONDA_PLL_FREQ_LOCK_DET BIT(29)
>
> This seems similar to ALPHA_PLL_ACK_LATCH..?
>
The bit is the same, and it is also used with wait_for_pll(), but the
meaning seems different (the usage pattern is different).
>> +const struct clk_ops clk_alpha_pll_postdiv_zonda_ops = {
>> + .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
>> + .round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
>> + .set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
>> +};
>> +EXPORT_SYMBOL(clk_alpha_pll_postdiv_zonda_ops);
>
> Why add one more ops when we can reuse clk_alpha_pll_postdiv_fabia_ops
> for this?
>
No reason (copied from downstream), will fix.
>> +
>> + /* Set operation mode to OFF */
>> + regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
>> +
>> + /* PLL should be in OFF mode before continuing */
>> + wmb();
>
> Why a barrier?
>
Again no reason (copied from downstream, but it doesn't make sense to
have this barrier).
>> +static unsigned long
>> +clk_zonda_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
>> +{
>> + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
>> + u32 l, frac;
>> +
>> + regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
>> + regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac);
>> +
>> + return alpha_pll_calc_rate(parent_rate, l, frac, ALPHA_BITWIDTH);
>> +}
>
> sounds like you could use clk_trion_pll_recalc_rate() instead
>
I had this thought as well, but alpha_width in
clk_trion_pll_recalc()_rate is 16, here ALPHA_BITWIDTH is 32, so I just
copied this from downstream.
I think changing pll_alpha_width() to return the right value for zonda
will work and allow sharing the function, if you think that's a good idea?
next prev parent reply other threads:[~2021-05-18 13:07 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-13 17:52 [PATCH 0/3] clk: qcom: Add camera clock controller driver for SM8250 Jonathan Marek
2021-05-13 17:52 ` [PATCH 1/3] clk: qcom: clk-alpha-pll: add support for zonda pll Jonathan Marek
2021-05-18 11:15 ` Robert Foss
2021-05-18 11:32 ` Vinod Koul
2021-05-18 13:06 ` Jonathan Marek [this message]
2021-05-18 15:56 ` Vinod Koul
2021-05-19 4:52 ` Taniya Das
2021-05-13 17:52 ` [PATCH 2/3] dt-bindings: clock: add QCOM SM8250 camera clock bindings Jonathan Marek
2021-05-14 13:06 ` Rob Herring
2021-05-13 17:52 ` [PATCH 3/3] clk: qcom: Add camera clock controller driver for SM8250 Jonathan Marek
2021-05-18 11:39 ` Vinod Koul
2021-05-18 11:42 ` Robert Foss
2021-05-18 12:35 ` Jonathan Marek
2021-05-18 12:41 ` Robert Foss
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