From: Stephen Boyd <sboyd@kernel.org>
To: Michael Turquette <mturquette@baylibre.com>,
Vinod Koul <vkoul@kernel.org>
Cc: Khasim Syed Mohammed <khasim.mohammed@linaro.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Taniya Das <tdas@codeaurora.org>,
Andy Gross <andy.gross@linaro.org>,
David Brown <david.brown@linaro.org>,
linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
Anu Ramanathan <anur@codeaurora.org>,
Shawn Guo <shawn.guo@linaro.org>, Vinod Koul <vkoul@kernel.org>
Subject: Re: [PATCH 2/2] clk: qcom: gcc-qcs404: Add cfg_offset for blsp1_uart3 clock
Date: Tue, 29 Jan 2019 14:42:57 -0800 [thread overview]
Message-ID: <154880177752.136743.5878273892342836134@swboyd.mtv.corp.google.com> (raw)
In-Reply-To: <20190128115359.30039-2-vkoul@kernel.org>
Quoting Vinod Koul (2019-01-28 03:53:59)
> diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c
> index 64da032bb9ed..493e055299b4 100644
> --- a/drivers/clk/qcom/gcc-qcs404.c
> +++ b/drivers/clk/qcom/gcc-qcs404.c
> @@ -678,6 +678,7 @@ static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
> .cmd_rcgr = 0x4014,
> .mnd_width = 16,
> .hid_width = 5,
> + .cfg_off = 0x20,
And it's one single clk! None of the other blsp clks have this problem?
> .parent_map = gcc_parent_map_0,
> .freq_tbl = ftbl_blsp1_uart0_apps_clk_src,
> .clkr.hw.init = &(struct clk_init_data){
next prev parent reply other threads:[~2019-01-29 22:44 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-28 11:53 [PATCH 1/2] clk: qcom: clk-rcg2: Introduce a cfg offset for RCGs Vinod Koul
2019-01-28 11:53 ` [PATCH 2/2] clk: qcom: gcc-qcs404: Add cfg_offset for blsp1_uart3 clock Vinod Koul
2019-01-29 22:42 ` Stephen Boyd [this message]
2019-01-29 22:42 ` [PATCH 1/2] clk: qcom: clk-rcg2: Introduce a cfg offset for RCGs Stephen Boyd
2019-01-30 4:34 ` Vinod Koul
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