From: Weiyi Lu <weiyi.lu@mediatek.com>
To: Matthias Brugger <matthias.bgg@gmail.com>,
Rob Herring <robh@kernel.org>, Stephen Boyd <sboyd@kernel.org>,
Nicolas Boichat <drinkcat@chromium.org>
Cc: James Liao <jamesjj.liao@mediatek.com>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>,
<linux-mediatek@lists.infradead.org>, <linux-clk@vger.kernel.org>,
<srv_heupstream@mediatek.com>, Weiyi Lu <weiyi.lu@mediatek.com>,
Wendell Lin <wendell.lin@mediatek.com>
Subject: [PATCH v2 4/5] clk: mediatek: Add configurable enable control to mtk_pll_data
Date: Wed, 29 Jul 2020 16:44:36 +0800 [thread overview]
Message-ID: <1596012277-8448-5-git-send-email-weiyi.lu@mediatek.com> (raw)
In-Reply-To: <1596012277-8448-1-git-send-email-weiyi.lu@mediatek.com>
In all MediaTek PLL design, bit0 of CON0 register is always
the enable bit.
However, there's a special case of usbpll on MT8192.
The enable bit of usbpll is moved to bit2 of other register.
Add configurable en_reg and pll_en_bit for enable control or
default 0 where pll data are static variables.
Hence, CON0_BASE_EN could also be removed.
And there might have another special case on other chips,
the enable bit is still on CON0 register but not at bit0.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
drivers/clk/mediatek/clk-mtk.h | 2 ++
drivers/clk/mediatek/clk-pll.c | 18 +++++++++++-------
2 files changed, 13 insertions(+), 7 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index c3d6756..810eb97 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -233,6 +233,8 @@ struct mtk_pll_data {
uint32_t pcw_chg_reg;
const struct mtk_pll_div_table *div_table;
const char *parent_name;
+ uint32_t en_reg;
+ uint8_t pll_en_bit;
};
void mtk_clk_register_plls(struct device_node *node,
diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
index 3c79e1a..1434e99 100644
--- a/drivers/clk/mediatek/clk-pll.c
+++ b/drivers/clk/mediatek/clk-pll.c
@@ -16,7 +16,6 @@
#define REG_CON0 0
#define REG_CON1 4
-#define CON0_BASE_EN BIT(0)
#define CON0_PWR_ON BIT(0)
#define CON0_ISO_EN BIT(1)
#define PCW_CHG_MASK BIT(31)
@@ -44,6 +43,7 @@ struct mtk_clk_pll {
void __iomem *tuner_en_addr;
void __iomem *pcw_addr;
void __iomem *pcw_chg_addr;
+ void __iomem *en_addr;
const struct mtk_pll_data *data;
};
@@ -56,7 +56,7 @@ static int mtk_pll_is_prepared(struct clk_hw *hw)
{
struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
- return (readl(pll->base_addr + REG_CON0) & CON0_BASE_EN) != 0;
+ return (readl(pll->en_addr) & BIT(pll->data->pll_en_bit)) != 0;
}
static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin,
@@ -247,8 +247,8 @@ static int mtk_pll_prepare(struct clk_hw *hw)
writel(r, pll->pwr_addr);
udelay(1);
- r = readl(pll->base_addr + REG_CON0) | CON0_BASE_EN;
- writel(r, pll->base_addr + REG_CON0);
+ r = readl(pll->en_addr) | BIT(pll->data->pll_en_bit);
+ writel(r, pll->en_addr);
r = readl(pll->base_addr + REG_CON0) | pll->data->en_mask;
writel(r, pll->base_addr + REG_CON0);
@@ -283,9 +283,9 @@ static void mtk_pll_unprepare(struct clk_hw *hw)
r &= ~pll->data->en_mask;
writel(r, pll->base_addr + REG_CON0);
- r = readl(pll->base_addr + REG_CON0);
- r &= ~CON0_BASE_EN;
- writel(r, pll->base_addr + REG_CON0);
+ r = readl(pll->en_addr);
+ r &= ~BIT(pll->data->pll_en_bit);
+ writel(r, pll->en_addr);
r = readl(pll->pwr_addr) | CON0_ISO_EN;
writel(r, pll->pwr_addr);
@@ -327,6 +327,10 @@ static struct clk *mtk_clk_register_pll(const struct mtk_pll_data *data,
pll->tuner_addr = base + data->tuner_reg;
if (data->tuner_en_reg)
pll->tuner_en_addr = base + data->tuner_en_reg;
+ if (data->en_reg)
+ pll->en_addr = base + data->en_reg;
+ else
+ pll->en_addr = pll->base_addr + REG_CON0;
pll->hw.init = &init;
pll->data = data;
--
1.8.1.1.dirty
next prev parent reply other threads:[~2020-07-29 8:44 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-29 8:44 [PATCH v2 0/5] Mediatek MT8192 clock support Weiyi Lu
2020-07-29 8:44 ` [PATCH v2 1/5] dt-bindings: ARM: Mediatek: Document bindings for MT8192 Weiyi Lu
2020-07-29 9:53 ` Enric Balletbo Serra
2020-08-11 7:01 ` Weiyi Lu
2020-07-29 8:44 ` [PATCH v2 2/5] clk: mediatek: Add dt-bindings for MT8192 clocks Weiyi Lu
2020-07-29 8:44 ` [PATCH v2 3/5] clk: mediatek: Fix asymmetrical PLL enable and disable control Weiyi Lu
2020-07-29 10:51 ` Nicolas Boichat
2020-07-29 11:02 ` Nicolas Boichat
2020-08-11 6:34 ` Weiyi Lu
2020-08-11 6:50 ` Weiyi Lu
2020-07-29 8:44 ` Weiyi Lu [this message]
2020-07-29 10:58 ` [PATCH v2 4/5] clk: mediatek: Add configurable enable control to mtk_pll_data Nicolas Boichat
2020-08-11 6:43 ` Weiyi Lu
2020-08-11 7:28 ` Nicolas Boichat
2020-08-11 9:31 ` Weiyi Lu
[not found] ` <1596012277-8448-6-git-send-email-weiyi.lu@mediatek.com>
2020-07-29 9:32 ` [PATCH v2 5/5] clk: mediatek: Add MT8192 clock support Enric Balletbo Serra
2020-08-11 7:03 ` Weiyi Lu
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1596012277-8448-5-git-send-email-weiyi.lu@mediatek.com \
--to=weiyi.lu@mediatek.com \
--cc=drinkcat@chromium.org \
--cc=jamesjj.liao@mediatek.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mediatek@lists.infradead.org \
--cc=matthias.bgg@gmail.com \
--cc=robh@kernel.org \
--cc=sboyd@kernel.org \
--cc=srv_heupstream@mediatek.com \
--cc=wendell.lin@mediatek.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).