From: Chen-Yu Tsai <wens@csie.org>
To: Maxime Ripard <maxime.ripard@bootlin.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>
Cc: Chen-Yu Tsai <wens@csie.org>,
linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org,
dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: [PATCH 08/11] ARM: dts: sun8i-a33: Move display pipeline nodes to a23/a33 common dtsi
Date: Fri, 25 Jan 2019 11:23:11 +0800 [thread overview]
Message-ID: <20190125032314.20915-9-wens@csie.org> (raw)
In-Reply-To: <20190125032314.20915-1-wens@csie.org>
The display pipeline has the same structure, resources and connections
on both the A23 and A33. The differences include:
- compatible strings
- extra clock, reset control, and IO region for SAT in the backend
only found on the A33
- missing ch1 clock for the TCON
However, while the A23 has the TCON ch1 clock defined in the CCU, and
the channel 1 registers are available, it does not have any means to
use channel 1 due to a lack of downstream encoders, and the enable bit
for channel 1 is hard-wired to 0 (off).
As the MIPI DSI output device is not officially documented, and there
are no A23 reference devices to test it, it is not covered by this
patch.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
arch/arm/boot/dts/sun8i-a23-a33.dtsi | 147 ++++++++++++++++++++
arch/arm/boot/dts/sun8i-a33.dtsi | 194 ++++++---------------------
2 files changed, 185 insertions(+), 156 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
index 97ec8b8cec09..43fe215e83ea 100644
--- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
@@ -68,6 +68,12 @@
};
};
+ de: display-engine {
+ /* compatible gets set in SoC specific dtsi file */
+ allwinner,pipelines = <&fe0>;
+ status = "disabled";
+ };
+
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
@@ -168,6 +174,42 @@
#size-cells = <0>;
};
+ tcon0: lcd-controller@1c0c000 {
+ /* compatible gets set in SoC specific dtsi file */
+ reg = <0x01c0c000 0x1000>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_LCD>,
+ <&ccu CLK_LCD_CH0>;
+ clock-names = "ahb",
+ "tcon-ch0";
+ clock-output-names = "tcon-pixel-clock";
+ resets = <&ccu RST_BUS_LCD>;
+ reset-names = "lcd";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon0_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ tcon0_in_drc0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&drc0_out_tcon0>;
+ };
+ };
+
+ tcon0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ };
+ };
+
mmc0: mmc@1c0f000 {
compatible = "allwinner,sun7i-a20-mmc";
reg = <0x01c0f000 0x1000>;
@@ -570,6 +612,111 @@
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
+ fe0: display-frontend@1e00000 {
+ /* compatible gets set in SoC specific dtsi file */
+ reg = <0x01e00000 0x20000>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>,
+ <&ccu CLK_DRAM_DE_FE>;
+ clock-names = "ahb", "mod",
+ "ram";
+ resets = <&ccu RST_BUS_DE_FE>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fe0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ fe0_out_be0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&be0_in_fe0>;
+ };
+ };
+ };
+ };
+
+ be0: display-backend@1e60000 {
+ /* compatible gets set in SoC specific dtsi file */
+ reg = <0x01e60000 0x10000>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,
+ <&ccu CLK_DRAM_DE_BE>;
+ clock-names = "ahb", "mod",
+ "ram";
+ resets = <&ccu RST_BUS_DE_BE>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ be0_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ be0_in_fe0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&fe0_out_be0>;
+ };
+ };
+
+ be0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ be0_out_drc0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&drc0_in_be0>;
+ };
+ };
+ };
+ };
+
+ drc0: drc@1e70000 {
+ /* compatible gets set in SoC specific dtsi file */
+ reg = <0x01e70000 0x10000>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_DRC>, <&ccu CLK_DRC>,
+ <&ccu CLK_DRAM_DRC>;
+ clock-names = "ahb", "mod", "ram";
+ resets = <&ccu RST_BUS_DRC>;
+
+ assigned-clocks = <&ccu CLK_DRC>;
+ assigned-clock-rates = <300000000>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ drc0_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ drc0_in_be0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&be0_out_drc0>;
+ };
+ };
+
+ drc0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ drc0_out_tcon0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&tcon0_in_drc0>;
+ };
+ };
+ };
+ };
+
rtc: rtc@1f00000 {
compatible = "allwinner,sun8i-a23-rtc";
reg = <0x01f00000 0x400>;
diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi
index 626152c30f50..1111a6498102 100644
--- a/arch/arm/boot/dts/sun8i-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a33.dtsi
@@ -159,12 +159,6 @@
};
};
- de: display-engine {
- compatible = "allwinner,sun8i-a33-display-engine";
- allwinner,pipelines = <&fe0>;
- status = "disabled";
- };
-
iio-hwmon {
compatible = "iio-hwmon";
io-channels = <&ths>;
@@ -209,47 +203,6 @@
};
soc {
- tcon0: lcd-controller@1c0c000 {
- compatible = "allwinner,sun8i-a33-tcon";
- reg = <0x01c0c000 0x1000>;
- interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_LCD>,
- <&ccu CLK_LCD_CH0>;
- clock-names = "ahb",
- "tcon-ch0";
- clock-output-names = "tcon-pixel-clock";
- resets = <&ccu RST_BUS_LCD>;
- reset-names = "lcd";
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- tcon0_in: port@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
-
- tcon0_in_drc0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&drc0_out_tcon0>;
- };
- };
-
- tcon0_out: port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
-
- tcon0_out_dsi: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&dsi_in_tcon0>;
- };
- };
- };
- };
-
video-codec@1c0e000 {
compatible = "allwinner,sun8i-a33-video-engine";
reg = <0x01c0e000 0x1000>;
@@ -339,115 +292,6 @@
status = "disabled";
#phy-cells = <0>;
};
-
- fe0: display-frontend@1e00000 {
- compatible = "allwinner,sun8i-a33-display-frontend";
- reg = <0x01e00000 0x20000>;
- interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>,
- <&ccu CLK_DRAM_DE_FE>;
- clock-names = "ahb", "mod",
- "ram";
- resets = <&ccu RST_BUS_DE_FE>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- fe0_out: port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
-
- fe0_out_be0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&be0_in_fe0>;
- };
- };
- };
- };
-
- be0: display-backend@1e60000 {
- compatible = "allwinner,sun8i-a33-display-backend";
- reg = <0x01e60000 0x10000>, <0x01e80000 0x1000>;
- reg-names = "be", "sat";
- interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,
- <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_BUS_SAT>;
- clock-names = "ahb", "mod",
- "ram", "sat";
- resets = <&ccu RST_BUS_DE_BE>, <&ccu RST_BUS_SAT>;
- reset-names = "be", "sat";
- assigned-clocks = <&ccu CLK_DE_BE>;
- assigned-clock-rates = <300000000>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- be0_in: port@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
-
- be0_in_fe0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&fe0_out_be0>;
- };
- };
-
- be0_out: port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
-
- be0_out_drc0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&drc0_in_be0>;
- };
- };
- };
- };
-
- drc0: drc@1e70000 {
- compatible = "allwinner,sun8i-a33-drc";
- reg = <0x01e70000 0x10000>;
- interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_DRC>, <&ccu CLK_DRC>,
- <&ccu CLK_DRAM_DRC>;
- clock-names = "ahb", "mod", "ram";
- resets = <&ccu RST_BUS_DRC>;
-
- assigned-clocks = <&ccu CLK_DRC>;
- assigned-clock-rates = <300000000>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- drc0_in: port@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
-
- drc0_in_be0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&be0_out_drc0>;
- };
- };
-
- drc0_out: port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
-
- drc0_out_tcon0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&tcon0_in_drc0>;
- };
- };
- };
- };
};
thermal-zones {
@@ -524,10 +368,37 @@
};
};
+&be0 {
+ compatible = "allwinner,sun8i-a33-display-backend";
+ /* A33 has an extra "SAT" module packed inside the display backend */
+ reg = <0x01e60000 0x10000>, <0x01e80000 0x1000>;
+ reg-names = "be", "sat";
+ clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,
+ <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_BUS_SAT>;
+ clock-names = "ahb", "mod",
+ "ram", "sat";
+ resets = <&ccu RST_BUS_DE_BE>, <&ccu RST_BUS_SAT>;
+ reset-names = "be", "sat";
+ assigned-clocks = <&ccu CLK_DE_BE>;
+ assigned-clock-rates = <300000000>;
+};
+
&ccu {
compatible = "allwinner,sun8i-a33-ccu";
};
+&de {
+ compatible = "allwinner,sun8i-a33-display-engine";
+};
+
+&drc0 {
+ compatible = "allwinner,sun8i-a33-drc";
+};
+
+&fe0 {
+ compatible = "allwinner,sun8i-a33-display-frontend";
+};
+
&mali {
operating-points-v2 = <&mali_opp_table>;
};
@@ -544,6 +415,17 @@
};
+&tcon0 {
+ compatible = "allwinner,sun8i-a33-tcon";
+};
+
+&tcon0_out {
+ tcon0_out_dsi: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&dsi_in_tcon0>;
+ };
+};
+
&usb_otg {
compatible = "allwinner,sun8i-a33-musb";
};
--
2.20.1
next prev parent reply other threads:[~2019-01-25 3:23 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-25 3:23 [PATCH 00/11] ARM: sun8i: a23: Enable display pipeline Chen-Yu Tsai
2019-01-25 3:23 ` [PATCH 01/11] clk: sunxi-ng: sun8i-a23: Enable PLL-MIPI LDOs when ungating it Chen-Yu Tsai
2019-01-28 9:11 ` Jagan Teki
2019-01-25 3:23 ` [PATCH 02/11] dt-bindings: display: sun4i-drm: Add compatible strings for A23 display Chen-Yu Tsai
2019-01-25 3:23 ` [PATCH 03/11] drm/sun4i: backend: Remove BGRX8888 from list of supported formats Chen-Yu Tsai
2019-01-25 3:23 ` [PATCH 04/11] drm/sun4i: layer: Assign backend pointer before calling DRM helpers Chen-Yu Tsai
2019-01-25 3:23 ` [PATCH 05/11] drm/sun4i: layer: support just backend formats when frontend is unavailable Chen-Yu Tsai
2019-01-25 3:23 ` [PATCH 06/11] drm/sun4i: Add support for A23 display pipeline Chen-Yu Tsai
2019-01-25 3:23 ` [PATCH 07/11] ARM: dts: sun8i-a23-a33: Move NAND controller device node to sort by address Chen-Yu Tsai
2019-01-25 3:23 ` Chen-Yu Tsai [this message]
2019-01-25 3:23 ` [PATCH 09/11] ARM: dts: sun8i-a23: Add compatible strings to display pipeline device nodes Chen-Yu Tsai
2019-01-25 3:23 ` [PATCH 10/11] ARM: dts: sun8i-q8-common: Enable display pipeline with RGB LCD panel Chen-Yu Tsai
2019-01-25 3:23 ` [PATCH 11/11] ARM: dts: sun8i-a23-q8: Set compatible string for " Chen-Yu Tsai
2019-01-25 9:44 ` [PATCH 00/11] ARM: sun8i: a23: Enable display pipeline Maxime Ripard
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20190125032314.20915-9-wens@csie.org \
--to=wens@csie.org \
--cc=airlied@linux.ie \
--cc=daniel@ffwll.ch \
--cc=devicetree@vger.kernel.org \
--cc=dri-devel@lists.freedesktop.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=mark.rutland@arm.com \
--cc=maxime.ripard@bootlin.com \
--cc=mturquette@baylibre.com \
--cc=robh+dt@kernel.org \
--cc=sboyd@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).