From: Tero Kristo <t-kristo@ti.com>
To: <linux-clk@vger.kernel.org>, <sboyd@kernel.org>,
<mturquette@baylibre.com>
Cc: <linux-omap@vger.kernel.org>, <tony@atomide.com>,
<aford173@gmail.com>, <tomi.valkeinen@ti.com>
Subject: [PATCH 0/4] clk: ti: re-work divider clock support
Date: Wed, 2 Oct 2019 15:06:07 +0300 [thread overview]
Message-ID: <20191002120611.26121-1-t-kristo@ti.com> (raw)
Hi,
The existing divider clock support appears to have an inherent bug
because of the bit field width implementation and limitation of divider
values based on this. The limitation by bit field only is not enough,
as we can have divider settings which accept only certain range of
dividers within the full range of the bit-field.
Because of this, the divider clock is re-implemented to use min,max,mask
values instead of just the bit-field.
-Tero
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
next reply other threads:[~2019-10-02 12:06 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-02 12:06 Tero Kristo [this message]
2019-10-02 12:06 ` [PATCH 1/4] clk: ti: divider: cleanup _register_divider and ti_clk_get_div_table Tero Kristo
2019-10-02 12:41 ` Adam Ford
2019-10-02 12:06 ` [PATCH 2/4] clk: ti: divider: cleanup ti_clk_parse_divider_data API Tero Kristo
2019-10-02 12:06 ` [PATCH 3/4] clk: ti: divider: convert to use min,max,mask instead of width Tero Kristo
2019-10-02 12:06 ` [PATCH 4/4] ARM: dts: omap3: fix DPLL4 M4 divider max value Tero Kristo
2019-10-24 8:03 ` [PATCH 0/4] clk: ti: re-work divider clock support Tero Kristo
2019-10-24 13:40 ` Tony Lindgren
2019-10-28 9:59 ` Stephen Boyd
2019-10-28 10:23 ` Tero Kristo
2019-10-28 11:36 ` Tomi Valkeinen
2019-10-28 13:57 ` Tony Lindgren
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