From: Stephen Boyd <sboyd@kernel.org>
To: Chunyan Zhang <chunyan.zhang@unisoc.com>,
Mark Rutland <mark.rutland@arm.com>,
Michael Turquette <mturquette@baylibre.com>,
Rob Herring <robh+dt@kernel.org>
Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, Orson Zhai <orsonzhai@gmail.com>,
Baolin Wang <baolin.wang7@gmail.com>,
Chunyan Zhang <zhang.lyra@gmail.com>,
Xiaolong Zhang <xiaolong.zhang@unisoc.com>,
Chunyan Zhang <chunyan.zhang@unisoc.com>
Subject: Re: [PATCH 1/5] clk: sprd: add gate for pll clocks
Date: Wed, 13 Nov 2019 14:15:28 -0800 [thread overview]
Message-ID: <20191113221530.5CAD9206E3@mail.kernel.org> (raw)
In-Reply-To: <20191025111338.27324-2-chunyan.zhang@unisoc.com>
Quoting Chunyan Zhang (2019-10-25 04:13:34)
> diff --git a/drivers/clk/sprd/gate.c b/drivers/clk/sprd/gate.c
> index f59d1936b412..d8b480f852f3 100644
> --- a/drivers/clk/sprd/gate.c
> +++ b/drivers/clk/sprd/gate.c
> @@ -109,3 +120,11 @@ const struct clk_ops sprd_sc_gate_ops = {
> };
> EXPORT_SYMBOL_GPL(sprd_sc_gate_ops);
>
> +#define sprd_pll_sc_gate_unprepare sprd_sc_gate_disable
Why is there a redefine? Just use the function where it is.
> +
> +const struct clk_ops sprd_pll_sc_gate_ops = {
> + .unprepare = sprd_pll_sc_gate_unprepare,
> + .prepare = sprd_pll_sc_gate_prepare,
> + .is_enabled = sprd_gate_is_enabled,
> +};
> +EXPORT_SYMBOL_GPL(sprd_pll_sc_gate_ops);
> diff --git a/drivers/clk/sprd/gate.h b/drivers/clk/sprd/gate.h
> index dc352ea55e1f..598ce607ca0a 100644
> --- a/drivers/clk/sprd/gate.h
> +++ b/drivers/clk/sprd/gate.h
> @@ -14,16 +14,19 @@ struct sprd_gate {
> u32 enable_mask;
> u16 flags;
> u16 sc_offset;
> + u32 udelay;
Does the delay need to be 32 bits wide? Maybe a u8 or u16 will work?
Otherwise, make it an unsigned long please because the bit width doesn't
matter.
next prev parent reply other threads:[~2019-11-13 22:15 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-25 11:13 [PATCH 0/5] Add clocks for Unisoc's SC9863A Chunyan Zhang
2019-10-25 11:13 ` [PATCH 1/5] clk: sprd: add gate for pll clocks Chunyan Zhang
2019-11-13 22:15 ` Stephen Boyd [this message]
2019-10-25 11:13 ` [PATCH 2/5] dt-bindings: clk: sprd: rename the common file name sprd.txt to SoC specific Chunyan Zhang
2019-10-29 21:46 ` Rob Herring
2019-10-25 11:13 ` [PATCH 3/5] dt-bindings: clk: sprd: add bindings for sc9863a clock controller Chunyan Zhang
2019-10-29 22:01 ` Rob Herring
2019-10-25 11:13 ` [PATCH 4/5] clk: sprd: Add dt-bindings include file for SC9863A Chunyan Zhang
2019-10-29 22:03 ` Rob Herring
2019-10-25 11:13 ` [PATCH 5/5] clk: sprd: add clocks support " Chunyan Zhang
2019-11-13 22:19 ` Stephen Boyd
2019-11-14 7:13 ` Chunyan Zhang
2019-11-17 11:27 ` Chunyan Zhang
2019-11-25 1:33 ` Stephen Boyd
2019-11-25 2:10 ` Chunyan Zhang
2019-11-25 16:35 ` Stephen Boyd
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