From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, UNWANTED_LANGUAGE_BODY,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E85D3C43215 for ; Tue, 3 Dec 2019 04:02:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C4EB1206E1 for ; Tue, 3 Dec 2019 04:02:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726592AbfLCECn (ORCPT ); Mon, 2 Dec 2019 23:02:43 -0500 Received: from pbmsgap02.intersil.com ([192.157.179.202]:53004 "EHLO pbmsgap02.intersil.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726327AbfLCECn (ORCPT ); Mon, 2 Dec 2019 23:02:43 -0500 Received: from pps.filterd (pbmsgap02.intersil.com [127.0.0.1]) by pbmsgap02.intersil.com (8.16.0.27/8.16.0.27) with SMTP id xB33ipI7008708; Mon, 2 Dec 2019 22:46:25 -0500 Received: from pbmxdp03.intersil.corp (pbmxdp03.pb.intersil.com [132.158.200.224]) by pbmsgap02.intersil.com with ESMTP id 2wkkffj009-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 02 Dec 2019 22:46:25 -0500 Received: from pbmxdp01.intersil.corp (132.158.200.222) by pbmxdp03.intersil.corp (132.158.200.224) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id 15.1.1531.3; Mon, 2 Dec 2019 22:46:24 -0500 Received: from localhost.localdomain (132.158.202.109) by pbmxdp01.intersil.corp (132.158.200.222) with Microsoft SMTP Server id 15.1.1531.3 via Frontend Transport; Mon, 2 Dec 2019 22:46:23 -0500 From: Chris Brandt To: Mark Brown , Rob Herring , "Mark Rutland" , Geert Uytterhoeven , Michael Turquette , Stephen Boyd CC: , , , , Mason Yang , Sergei Shtylyov , Chris Brandt Subject: [PATCH 3/6] clk: renesas: r7s9210: Add SPIBSC clock Date: Mon, 2 Dec 2019 22:45:16 -0500 Message-ID: <20191203034519.5640-4-chris.brandt@renesas.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191203034519.5640-1-chris.brandt@renesas.com> References: <20191203034519.5640-1-chris.brandt@renesas.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7BIT Content-Type: text/plain; charset=US-ASCII X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2019-12-02_06:,, signatures=0 X-Proofpoint-Spam-Details: rule=junk_notspam policy=junk score=0 suspectscore=2 malwarescore=0 phishscore=0 bulkscore=0 spamscore=0 mlxscore=0 mlxlogscore=888 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1911200000 definitions=main-1912030031 X-Proofpoint-Spam-Reason: mlx Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The SPIBSC clocks are marked as critical because for XIP systems, the kernel will be running from QSPI flash and cannot be turned off. Signed-off-by: Chris Brandt --- drivers/clk/renesas/r7s9210-cpg-mssr.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/clk/renesas/r7s9210-cpg-mssr.c b/drivers/clk/renesas/r7s9210-cpg-mssr.c index 14093503c085..153d3a49eee0 100644 --- a/drivers/clk/renesas/r7s9210-cpg-mssr.c +++ b/drivers/clk/renesas/r7s9210-cpg-mssr.c @@ -93,6 +93,7 @@ static const struct mssr_mod_clk r7s9210_mod_clks[] __initconst = { DEF_MOD_STB("ether1", 64, R7S9210_CLK_B), DEF_MOD_STB("ether0", 65, R7S9210_CLK_B), + DEF_MOD_STB("spibsc", 83, R7S9210_CLK_P1), DEF_MOD_STB("i2c3", 84, R7S9210_CLK_P1), DEF_MOD_STB("i2c2", 85, R7S9210_CLK_P1), DEF_MOD_STB("i2c1", 86, R7S9210_CLK_P1), @@ -112,6 +113,10 @@ static const struct mssr_mod_clk r7s9210_mod_clks[] __initconst = { DEF_MOD_STB("vdc6", 81, R7S9210_CLK_P1), }; +static const unsigned int r7s9210_crit_mod_clks[] __initconst = { + MOD_CLK_ID_10(83), /* SPIBSC */ +}; + /* The clock dividers in the table vary based on DT and register settings */ static void __init r7s9210_update_clk_table(struct clk *extal_clk, void __iomem *base) @@ -213,6 +218,10 @@ const struct cpg_mssr_info r7s9210_cpg_mssr_info __initconst = { .num_mod_clks = ARRAY_SIZE(r7s9210_mod_clks), .num_hw_mod_clks = 11 * 32, /* includes STBCR0 which doesn't exist */ + /* Critical Module Clocks */ + .crit_mod_clks = r7s9210_crit_mod_clks, + .num_crit_mod_clks = ARRAY_SIZE(r7s9210_crit_mod_clks), + /* Callbacks */ .cpg_clk_register = rza2_cpg_clk_register, -- 2.23.0