From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
To: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Geert Uytterhoeven <geert+renesas@glider.be>,
linux-clk <linux-clk@vger.kernel.org>
Subject: Re: [PATCH] clk: renesas: r8a77980-cpg-mssr: fix RPC-IF module clock's parent
Date: Mon, 11 Mar 2019 20:14:23 +0300 [thread overview]
Message-ID: <981d0e06-76b8-fe69-1a8e-91661ad0faba@cogentembedded.com> (raw)
In-Reply-To: <CAMuHMdWxkM2YbLqyz3BemcVJphWYSZi4ejuLiG+fpfDdnuU4Uw@mail.gmail.com>
On 03/11/2019 12:30 PM, Geert Uytterhoeven wrote:
>> Testing has shown that the RPC-IF module clock's parent is the RPCD2 clock,
>> not the RPC one -- the RPC-IF register reads stall otherwise...
>
> Perhaps... Or something else is wrong with how the RPC driver uses the
> clock hierarchy.
Yes, explicitly enabling RPCD2 did help as well.
> According to the docs, RPC clocks RPC-PHY, and RPCD2 clocks RPC-LINK.
I've also read the manual. Note it's not that reading a PHY register
hangs the kernel but reading CMNCR...
> Currently nothing references RPCD2, so it is disabled automatically.
Only on V3H.
> If you make RPC -> RPCD2 -> RPC-IF, enabling RPC-IF indeed enables
> both RPC and RPCD2.
Sure, it does. :-)
> Perhaps the RPC device node does need a reference to RPCD2?
Looks like that wouldn't hurt either...
> Is this also the case on R-Car V3M, where RPCD2 is not controlled by the
> CPG, but by the DIVREG register in the RPC-IF module itself?
No hangs were seen on V3M, despite the RPCD2 clock remained disabled.
The RPC clocks on both V3H and V3M suffer from a lack of clear documentation...
> See also section 62.4.7 (Frequency change), which does not have a
> subsection for V3H, but it may be impacted (changing RPCD2 causes
> an additional read of RPCCKR, satisfying the read-after-write requirement
> documented there).
Hmm, haven't seen this item before; it looks like we can't use the standard
divider component. BTW, this section in the 1.50 manual tells to use the soft
reset on V3MOK. OK, I'll investigate this...
>> Fixes: 94e3935b5756 ("clk: renesas: r8a77980: Add RPC clocks")
>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
[...]
MBR, Sergei
next prev parent reply other threads:[~2019-03-11 17:14 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-22 19:55 [PATCH v3 0/4] Renesas R8A77980 CPG/MSSR RPC clock support Sergei Shtylyov
2019-01-22 19:57 ` [PATCH v3 1/4] clk: renesas: rcar-gen3-cpg: factor out cpg_reg_modify() Sergei Shtylyov
2019-01-22 19:58 ` [PATCH v3 2/4] clk: renesas: rcar-gen3-cpg: add spinlock Sergei Shtylyov
2019-01-22 19:59 ` [PATCH v3 3/4] clk: renesas: rcar-gen3-cpg: add RPC clocks Sergei Shtylyov
2019-01-25 10:25 ` Geert Uytterhoeven
2019-01-22 20:01 ` [PATCH v3 4/4] clk: renesas: r8a77980-cpg-mssr: " Sergei Shtylyov
2019-01-25 10:25 ` [PATCH v3 0/4] Renesas R8A77980 CPG/MSSR RPC clock support Geert Uytterhoeven
2019-03-07 19:53 ` [PATCH] clk: renesas: r8a77980-cpg-mssr: fix RPC-IF module clock's parent Sergei Shtylyov
2019-03-11 9:30 ` Geert Uytterhoeven
2019-03-11 17:14 ` Sergei Shtylyov [this message]
2019-03-11 19:10 ` Sergei Shtylyov
2019-09-27 18:09 ` [PATCH] clk: renesas: rcar-gen3: allow changing the RPC[D2] clocks Sergei Shtylyov
2019-10-07 11:45 ` Geert Uytterhoeven
2019-10-07 11:49 ` Sergei Shtylyov
2019-12-17 20:43 ` Geert Uytterhoeven
2019-12-18 19:34 ` Sergei Shtylyov
2019-12-20 14:31 ` Geert Uytterhoeven
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