From: Shukun Tan <tanshukun1@huawei.com>
To: <herbert@gondor.apana.org.au>, <davem@davemloft.net>
Cc: <linux-crypto@vger.kernel.org>, <xuzaibo@huawei.com>,
<wangzhou1@hisilicon.com>
Subject: [PATCH v2 01/12] crypto: hisilicon/sec2 - modify the SEC probe process
Date: Sat, 9 May 2020 17:43:54 +0800 [thread overview]
Message-ID: <1589017445-15514-2-git-send-email-tanshukun1@huawei.com> (raw)
In-Reply-To: <1589017445-15514-1-git-send-email-tanshukun1@huawei.com>
From: Longfang Liu <liulongfang@huawei.com>
Adjust the position of SMMU status check and
SEC queue initialization in SEC probe
Signed-off-by: Longfang Liu <liulongfang@huawei.com>
Signed-off-by: Zaibo Xu <xuzaibo@huawei.com>
Signed-off-by: Shukun Tan <tanshukun1@huawei.com>
Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com>
---
drivers/crypto/hisilicon/sec2/sec_main.c | 67 ++++++++++++++------------------
1 file changed, 30 insertions(+), 37 deletions(-)
diff --git a/drivers/crypto/hisilicon/sec2/sec_main.c b/drivers/crypto/hisilicon/sec2/sec_main.c
index 07a5f4e..ea029e3 100644
--- a/drivers/crypto/hisilicon/sec2/sec_main.c
+++ b/drivers/crypto/hisilicon/sec2/sec_main.c
@@ -765,6 +765,21 @@ static int sec_qm_init(struct hisi_qm *qm, struct pci_dev *pdev)
qm->dev_name = sec_name;
qm->fun_type = (pdev->device == SEC_PF_PCI_DEVICE_ID) ?
QM_HW_PF : QM_HW_VF;
+ if (qm->fun_type == QM_HW_PF) {
+ qm->qp_base = SEC_PF_DEF_Q_BASE;
+ qm->qp_num = pf_q_num;
+ qm->debug.curr_qm_qp_num = pf_q_num;
+ qm->qm_list = &sec_devices;
+ } else if (qm->fun_type == QM_HW_VF && qm->ver == QM_HW_V1) {
+ /*
+ * have no way to get qm configure in VM in v1 hardware,
+ * so currently force PF to uses SEC_PF_DEF_Q_NUM, and force
+ * to trigger only one VF in v1 hardware.
+ * v2 hardware has no such problem.
+ */
+ qm->qp_base = SEC_PF_DEF_Q_NUM;
+ qm->qp_num = SEC_QUEUE_NUM_V1 - SEC_PF_DEF_Q_NUM;
+ }
qm->use_dma_api = true;
return hisi_qm_init(qm);
@@ -775,8 +790,9 @@ static void sec_qm_uninit(struct hisi_qm *qm)
hisi_qm_uninit(qm);
}
-static int sec_probe_init(struct hisi_qm *qm, struct sec_dev *sec)
+static int sec_probe_init(struct sec_dev *sec)
{
+ struct hisi_qm *qm = &sec->qm;
int ret;
/*
@@ -793,40 +809,18 @@ static int sec_probe_init(struct hisi_qm *qm, struct sec_dev *sec)
return -ENOMEM;
}
- if (qm->fun_type == QM_HW_PF) {
- qm->qp_base = SEC_PF_DEF_Q_BASE;
- qm->qp_num = pf_q_num;
- qm->debug.curr_qm_qp_num = pf_q_num;
- qm->qm_list = &sec_devices;
-
+ if (qm->fun_type == QM_HW_PF)
ret = sec_pf_probe_init(sec);
- if (ret)
- goto err_probe_uninit;
- } else if (qm->fun_type == QM_HW_VF) {
- /*
- * have no way to get qm configure in VM in v1 hardware,
- * so currently force PF to uses SEC_PF_DEF_Q_NUM, and force
- * to trigger only one VF in v1 hardware.
- * v2 hardware has no such problem.
- */
- if (qm->ver == QM_HW_V1) {
- qm->qp_base = SEC_PF_DEF_Q_NUM;
- qm->qp_num = SEC_QUEUE_NUM_V1 - SEC_PF_DEF_Q_NUM;
- } else if (qm->ver == QM_HW_V2) {
- /* v2 starts to support get vft by mailbox */
- ret = hisi_qm_get_vft(qm, &qm->qp_base, &qm->qp_num);
- if (ret)
- goto err_probe_uninit;
- }
- } else {
- ret = -ENODEV;
- goto err_probe_uninit;
+ else if (qm->fun_type == QM_HW_VF && qm->ver == QM_HW_V2)
+ /* v2 starts to support get vft by mailbox */
+ ret = hisi_qm_get_vft(qm, &qm->qp_base, &qm->qp_num);
+
+ if (ret) {
+ destroy_workqueue(qm->wq);
+ return ret;
}
return 0;
-err_probe_uninit:
- destroy_workqueue(qm->wq);
- return ret;
}
static void sec_probe_uninit(struct hisi_qm *qm)
@@ -865,18 +859,17 @@ static int sec_probe(struct pci_dev *pdev, const struct pci_device_id *id)
pci_set_drvdata(pdev, sec);
- sec->ctx_q_num = ctx_q_num;
- sec_iommu_used_check(sec);
-
qm = &sec->qm;
-
ret = sec_qm_init(qm, pdev);
if (ret) {
- pci_err(pdev, "Failed to pre init qm!\n");
+ pci_err(pdev, "Failed to init SEC QM (%d)!\n", ret);
return ret;
}
- ret = sec_probe_init(qm, sec);
+ sec->ctx_q_num = ctx_q_num;
+ sec_iommu_used_check(sec);
+
+ ret = sec_probe_init(sec);
if (ret) {
pci_err(pdev, "Failed to probe!\n");
goto err_qm_uninit;
--
2.7.4
next prev parent reply other threads:[~2020-05-09 9:45 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-09 9:43 [PATCH v2 00/12] crypto: hisilicon - misc cleanup and optimizations Shukun Tan
2020-05-09 9:43 ` Shukun Tan [this message]
2020-05-09 9:43 ` [PATCH v2 02/12] crypto: hisilicon/hpre - modify the HPRE probe process Shukun Tan
2020-05-09 9:43 ` [PATCH v2 03/12] crypto: hisilicon/zip - modify the ZIP " Shukun Tan
2020-05-09 9:43 ` [PATCH v2 04/12] crypto: hisilicon - refactor module parameter pf_q_num related code Shukun Tan
2020-05-09 9:43 ` [PATCH v2 05/12] crypto: hisilicon/qm - add state machine for QM Shukun Tan
2020-05-09 9:43 ` [PATCH v2 06/12] crypto: hisilicon - add FLR support Shukun Tan
2020-05-09 9:44 ` [PATCH v2 07/12] crypto: hisilicon - remove use_dma_api related codes Shukun Tan
2020-05-09 9:44 ` [PATCH v2 08/12] crypto: hisilicon - unify initial value assignment into QM Shukun Tan
2020-05-09 9:44 ` [PATCH v2 09/12] crypto: hisilicon - QM memory management optimization Shukun Tan
2020-05-09 9:44 ` [PATCH v2 10/12] crypto: hisilicon - remove codes of directly report device errors through MSI Shukun Tan
2020-05-09 9:44 ` [PATCH v2 11/12] crypto: hisilicon - add device error report through abnormal irq Shukun Tan
2020-05-09 9:44 ` [PATCH v2 12/12] crypto: hisilicon/zip - Use temporary sqe when doing work Shukun Tan
2020-05-15 6:21 ` [PATCH v2 00/12] crypto: hisilicon - misc cleanup and optimizations Herbert Xu
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