From: Bjorn Helgaas <helgaas@kernel.org>
To: Zhou Wang <wangzhou1@hisilicon.com>
Cc: Zhangfei Gao <zhangfei.gao@linaro.org>,
Arnd Bergmann <arnd@arndb.de>, Joerg Roedel <joro@8bytes.org>,
Bjorn Helgaas <bhelgaas@google.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Hanjun Guo <guohanjun@huawei.com>,
Sudeep Holla <sudeep.holla@arm.com>,
"Rafael J. Wysocki" <rjw@rjwysocki.net>,
Len Brown <lenb@kernel.org>,
jean-philippe <jean-philippe@linaro.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Herbert Xu <herbert@gondor.apana.org.au>,
kenneth-lee-2012@foxmail.com,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"open list:HARDWARE RANDOM NUMBER GENERATOR CORE"
<linux-crypto@vger.kernel.org>,
"open list:IOMMU DRIVERS" <iommu@lists.linux-foundation.org>,
ACPI Devel Maling List <linux-acpi@vger.kernel.org>,
Linux ARM <linux-arm-kernel@lists.infradead.org>,
linux-pci <linux-pci@vger.kernel.org>,
Thanu Rangarajan <Thanu.Rangarajan@arm.com>,
Souvik Chakravarty <Souvik.Chakravarty@arm.com>,
wanghuiqiang <wanghuiqiang@huawei.com>
Subject: Re: [PATCH 0/2] Introduce PCI_FIXUP_IOMMU
Date: Thu, 17 Dec 2020 14:38:06 -0600 [thread overview]
Message-ID: <20201217203806.GA20785@bjorn-Precision-5520> (raw)
In-Reply-To: <5FD9EE6E.1040505@hisilicon.com>
On Wed, Dec 16, 2020 at 07:24:30PM +0800, Zhou Wang wrote:
> On 2020/6/23 23:04, Bjorn Helgaas wrote:
> > On Fri, Jun 19, 2020 at 10:26:54AM +0800, Zhangfei Gao wrote:
> >> Have studied _DSM method, two issues we met comparing using quirk.
> >>
> >> 1. Need change definition of either pci_host_bridge or pci_dev, like adding
> >> member can_stall,
> >> while pci system does not know stall now.
> >>
> >> a, pci devices do not have uuid: uuid need be described in dsdt, while pci
> >> devices are not defined in dsdt.
> >> so we have to use host bridge.
> >
> > PCI devices *can* be described in the DSDT. IIUC these particular
> > devices are hardwired (not plug-in cards), so platform firmware can
> > know about them and could describe them in the DSDT.
> >
> >> b, Parsing dsdt is in in pci subsystem.
> >> Like drivers/acpi/pci_root.c:
> >> obj = acpi_evaluate_dsm(ACPI_HANDLE(bus->bridge), &pci_acpi_dsm_guid,
> >> 1,
> >> IGNORE_PCI_BOOT_CONFIG_DSM, NULL);
> >>
> >> After parsing DSM in pci, we need record this info.
> >> Currently, can_stall info is recorded in iommu_fwspec,
> >> which is allocated in iommu_fwspec_init and called by iort_iommu_configure
> >> for uefi.
> >
> > You can look for a _DSM wherever it is convenient for you. It could
> > be in an AMBA shim layer.
> >
> >> 2. Guest kernel also need support sva.
> >> Using quirk, the guest can boot with sva enabled, since quirk is
> >> self-contained by kernel.
> >> If using _DSM, a specific uefi or dtb has to be provided,
> >> currently we can useQEMU_EFI.fd from apt install qemu-efi
> >
> > I don't quite understand what this means, but as I mentioned before, a
> > quirk for a *limited* number of devices is OK, as long as there is a
> > plan that removes the need for a quirk for future devices.
> >
> > E.g., if the next platform version ships with a DTB or firmware with a
> > _DSM or other mechanism that enables the kernel to discover this
> > information without a kernel change, it's fine to use a quirk to cover
> > the early platform.
> >
> > The principles are:
> >
> > - I don't want to have to update a quirk for every new Device ID
> > that needs this.
>
> Hi Bjorn and Zhangfei,
>
> We plan to use ATS/PRI to support SVA in future PCI devices. However, for
> current devices, we need to add limited number of quirk to let them
> work. The device IDs of current quirk needed devices are ZIP engine(0xa250, 0xa251),
> SEC engine(0xa255, 0xa256), HPRE engine(0xa258, 0xa259), revision id are
> 0x21 and 0x30.
>
> Let's continue to upstream these quirks!
Please post the patches you propose. I don't think the previous ones
are in my queue. Please include the lore URL for the previous
posting(s) in the cover letter so we can connect the discussion.
> > - I don't really want to have to manage non-PCI information in the
> > struct pci_dev. If this is AMBA- or IOMMU-related, it should be
> > stored in a structure related to AMBA or the IOMMU.
> > .
> >
next prev parent reply other threads:[~2020-12-17 20:39 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-26 11:49 [PATCH 0/2] Introduce PCI_FIXUP_IOMMU Zhangfei Gao
2020-05-26 11:49 ` [PATCH 1/2] PCI: " Zhangfei Gao
2020-05-26 14:46 ` Christoph Hellwig
2020-05-26 15:09 ` Zhangfei Gao
2020-05-27 9:01 ` Greg Kroah-Hartman
2020-05-26 11:49 ` [PATCH 2/2] iommu: calling pci_fixup_iommu in iommu_fwspec_init Zhangfei Gao
2020-05-27 9:01 ` Greg Kroah-Hartman
2020-05-28 6:53 ` Zhangfei Gao
2020-05-27 9:00 ` [PATCH 0/2] Introduce PCI_FIXUP_IOMMU Greg Kroah-Hartman
2020-05-27 9:53 ` Arnd Bergmann
2020-05-27 13:51 ` Zhangfei Gao
2020-05-27 18:18 ` Bjorn Helgaas
2020-05-28 6:46 ` Zhangfei Gao
2020-05-28 7:33 ` Joerg Roedel
2020-06-01 17:41 ` Bjorn Helgaas
2020-06-04 13:33 ` Zhangfei Gao
2020-06-05 23:19 ` Bjorn Helgaas
2020-06-08 2:54 ` Zhangfei Gao
2020-06-08 16:41 ` Bjorn Helgaas
2020-06-09 4:01 ` Zhangfei Gao
2020-06-09 9:15 ` Arnd Bergmann
2020-06-09 16:49 ` Bjorn Helgaas
2020-06-11 2:54 ` Zhangfei Gao
2020-06-11 13:44 ` Bjorn Helgaas
2020-06-13 14:30 ` Zhangfei Gao
2020-06-15 23:52 ` Bjorn Helgaas
2020-06-19 2:26 ` Zhangfei Gao
2020-06-23 15:04 ` Bjorn Helgaas
2020-12-16 11:24 ` Zhou Wang
2020-12-17 20:38 ` Bjorn Helgaas [this message]
2020-06-22 11:55 ` Joerg Roedel
2020-06-23 7:48 ` Zhangfei Gao
2020-06-22 11:53 ` Joerg Roedel
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