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Tue, 11 Feb 2020 02:59:28 -0500 Received: by mail-pg1-f195.google.com with SMTP id l24so5292979pgk.2 for ; Mon, 10 Feb 2020 23:59:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-transfer-encoding:content-language; bh=vgfeWj4AjQyurf0xeK1Z635NiCQf4E21yKLT1OZCOxI=; b=ri9VQfWjEpKz6UthsEkXDqvnC/vLM4tNXqWeNUw5XE4gn0yaVJfZkwQx4Sur/04JIb dRI4HjhUXnEFs97ZzjuEffQhpy0By2DTATHsRhkAXqVliZZ4fHIwvWPO5TnQeWDUnLZg TRdgI1Ei0NaaMFLHz8RAGH1G/K0sLzpTYyeoHEtYXyoujCLG0HHwpVteQX1xyBgglG0+ mB94kh5J+PtLDyeXSmXcseUkKQaf9div3/bJktotIn/0JC76R+oUZmJMIuHKE35UF3fF QxxODrdCPPoiz3b3F+66ptTJbFyHIjbsYgGQ9LW4NL086BNGPr2bgIO54+RBmMXNQJWz 7MbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-transfer-encoding :content-language; bh=vgfeWj4AjQyurf0xeK1Z635NiCQf4E21yKLT1OZCOxI=; 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Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: <20200210233711.GA1787983@kroah.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Content-Language: en-US Sender: linux-crypto-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org On 2020/2/11 上午7:37, Greg Kroah-Hartman wrote: > On Wed, Jan 15, 2020 at 10:12:46PM +0800, Zhangfei Gao wrote: >> From: Kenneth Lee >> >> Uacce (Unified/User-space-access-intended Accelerator Framework) targets to >> provide Shared Virtual Addressing (SVA) between accelerators and processes. >> So accelerator can access any data structure of the main cpu. >> This differs from the data sharing between cpu and io device, which share >> only data content rather than address. >> Since unified address, hardware and user space of process can share the >> same virtual address in the communication. >> >> Uacce create a chrdev for every registration, the queue is allocated to >> the process when the chrdev is opened. Then the process can access the >> hardware resource by interact with the queue file. By mmap the queue >> file space to user space, the process can directly put requests to the >> hardware without syscall to the kernel space. >> >> The IOMMU core only tracks mm<->device bonds at the moment, because it >> only needs to handle IOTLB invalidation and PASID table entries. However >> uacce needs a finer granularity since multiple queues from the same >> device can be bound to an mm. When the mm exits, all bound queues must >> be stopped so that the IOMMU can safely clear the PASID table entry and >> reallocate the PASID. >> >> An intermediate struct uacce_mm links uacce devices and queues. >> Note that an mm may be bound to multiple devices but an uacce_mm >> structure only ever belongs to a single device, because we don't need >> anything more complex (if multiple devices are bound to one mm, then >> we'll create one uacce_mm for each bond). >> >> uacce_device --+-- uacce_mm --+-- uacce_queue >> | '-- uacce_queue >> | >> '-- uacce_mm --+-- uacce_queue >> +-- uacce_queue >> '-- uacce_queue >> >> Reviewed-by: Jonathan Cameron >> Signed-off-by: Kenneth Lee >> Signed-off-by: Zaibo Xu >> Signed-off-by: Zhou Wang >> Signed-off-by: Jean-Philippe Brucker >> Signed-off-by: Zhangfei Gao > Looks much saner now, thanks for all of the work on this: > > Reviewed-by: Greg Kroah-Hartman > > Or am I supposed to take this in my tree? If so, I can, but I need an > ack for the crypto parts. > > That's Great, thanks Greg. For the convenience, I rebase the patchset on 5.6-rc1. Not sure is there any conflict to crypto tree. How about just pick the uacce part, patch 1 , 2. We can resend the crypto part to crypto tree. Thanks