From: guoren@kernel.org
To: guoren@kernel.org
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-csky@vger.kernel.org, linux-arch@vger.kernel.org,
Michael Clark <michaeljclark@mac.com>,
Peter Zijlstra <peterz@infradead.org>,
Anup Patel <anup@brainfault.org>, Arnd Bergmann <arnd@arndb.de>,
Palmer Dabbelt <palmerdabbelt@google.com>
Subject: [PATCH v4 4/4] riscv: Convert custom spinlock/rwlock to generic qspinlock/qrwlock
Date: Sat, 27 Mar 2021 18:06:39 +0000 [thread overview]
Message-ID: <1616868399-82848-5-git-send-email-guoren@kernel.org> (raw)
In-Reply-To: <1616868399-82848-1-git-send-email-guoren@kernel.org>
From: Michael Clark <michaeljclark@mac.com>
Update the RISC-V port to use the generic qspinlock and qrwlock.
This patch requires support for xchg for short which are added by
a previous patch.
Guo fixed up compile error which made by below include sequence:
+#include <asm/qrwlock.h>
+#include <asm/qspinlock.h>
Signed-off-by: Michael Clark <michaeljclark@mac.com>
Co-developed-by: Guo Ren <guoren@linux.alibaba.com>
Tested-by: Guo Ren <guoren@linux.alibaba.com>
Link: https://lore.kernel.org/linux-riscv/20190211043829.30096-3-michaeljclark@mac.com/
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Anup Patel <anup@brainfault.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Palmer Dabbelt <palmerdabbelt@google.com>
---
arch/riscv/Kconfig | 3 +
arch/riscv/include/asm/Kbuild | 3 +
arch/riscv/include/asm/spinlock.h | 126 +-----------------------
arch/riscv/include/asm/spinlock_types.h | 15 +--
4 files changed, 11 insertions(+), 136 deletions(-)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 87d7b52f278f..67cc65ba1ea1 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -33,6 +33,9 @@ config RISCV
select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
select ARCH_WANT_FRAME_POINTERS
select ARCH_WANT_HUGE_PMD_SHARE if 64BIT
+ select ARCH_USE_QUEUED_RWLOCKS
+ select ARCH_USE_QUEUED_SPINLOCKS
+ select ARCH_USE_QUEUED_SPINLOCKS_XCHG32
select CLONE_BACKWARDS
select CLINT_TIMER if !MMU
select COMMON_CLK
diff --git a/arch/riscv/include/asm/Kbuild b/arch/riscv/include/asm/Kbuild
index 445ccc97305a..750c1056b90f 100644
--- a/arch/riscv/include/asm/Kbuild
+++ b/arch/riscv/include/asm/Kbuild
@@ -3,5 +3,8 @@ generic-y += early_ioremap.h
generic-y += extable.h
generic-y += flat.h
generic-y += kvm_para.h
+generic-y += mcs_spinlock.h
+generic-y += qrwlock.h
+generic-y += qspinlock.h
generic-y += user.h
generic-y += vmlinux.lds.h
diff --git a/arch/riscv/include/asm/spinlock.h b/arch/riscv/include/asm/spinlock.h
index f4f7fa1b7ca8..a557de67a425 100644
--- a/arch/riscv/include/asm/spinlock.h
+++ b/arch/riscv/include/asm/spinlock.h
@@ -7,129 +7,7 @@
#ifndef _ASM_RISCV_SPINLOCK_H
#define _ASM_RISCV_SPINLOCK_H
-#include <linux/kernel.h>
-#include <asm/current.h>
-#include <asm/fence.h>
-
-/*
- * Simple spin lock operations. These provide no fairness guarantees.
- */
-
-/* FIXME: Replace this with a ticket lock, like MIPS. */
-
-#define arch_spin_is_locked(x) (READ_ONCE((x)->lock) != 0)
-
-static inline void arch_spin_unlock(arch_spinlock_t *lock)
-{
- smp_store_release(&lock->lock, 0);
-}
-
-static inline int arch_spin_trylock(arch_spinlock_t *lock)
-{
- int tmp = 1, busy;
-
- __asm__ __volatile__ (
- " amoswap.w %0, %2, %1\n"
- RISCV_ACQUIRE_BARRIER
- : "=r" (busy), "+A" (lock->lock)
- : "r" (tmp)
- : "memory");
-
- return !busy;
-}
-
-static inline void arch_spin_lock(arch_spinlock_t *lock)
-{
- while (1) {
- if (arch_spin_is_locked(lock))
- continue;
-
- if (arch_spin_trylock(lock))
- break;
- }
-}
-
-/***********************************************************/
-
-static inline void arch_read_lock(arch_rwlock_t *lock)
-{
- int tmp;
-
- __asm__ __volatile__(
- "1: lr.w %1, %0\n"
- " bltz %1, 1b\n"
- " addi %1, %1, 1\n"
- " sc.w %1, %1, %0\n"
- " bnez %1, 1b\n"
- RISCV_ACQUIRE_BARRIER
- : "+A" (lock->lock), "=&r" (tmp)
- :: "memory");
-}
-
-static inline void arch_write_lock(arch_rwlock_t *lock)
-{
- int tmp;
-
- __asm__ __volatile__(
- "1: lr.w %1, %0\n"
- " bnez %1, 1b\n"
- " li %1, -1\n"
- " sc.w %1, %1, %0\n"
- " bnez %1, 1b\n"
- RISCV_ACQUIRE_BARRIER
- : "+A" (lock->lock), "=&r" (tmp)
- :: "memory");
-}
-
-static inline int arch_read_trylock(arch_rwlock_t *lock)
-{
- int busy;
-
- __asm__ __volatile__(
- "1: lr.w %1, %0\n"
- " bltz %1, 1f\n"
- " addi %1, %1, 1\n"
- " sc.w %1, %1, %0\n"
- " bnez %1, 1b\n"
- RISCV_ACQUIRE_BARRIER
- "1:\n"
- : "+A" (lock->lock), "=&r" (busy)
- :: "memory");
-
- return !busy;
-}
-
-static inline int arch_write_trylock(arch_rwlock_t *lock)
-{
- int busy;
-
- __asm__ __volatile__(
- "1: lr.w %1, %0\n"
- " bnez %1, 1f\n"
- " li %1, -1\n"
- " sc.w %1, %1, %0\n"
- " bnez %1, 1b\n"
- RISCV_ACQUIRE_BARRIER
- "1:\n"
- : "+A" (lock->lock), "=&r" (busy)
- :: "memory");
-
- return !busy;
-}
-
-static inline void arch_read_unlock(arch_rwlock_t *lock)
-{
- __asm__ __volatile__(
- RISCV_RELEASE_BARRIER
- " amoadd.w x0, %1, %0\n"
- : "+A" (lock->lock)
- : "r" (-1)
- : "memory");
-}
-
-static inline void arch_write_unlock(arch_rwlock_t *lock)
-{
- smp_store_release(&lock->lock, 0);
-}
+#include <asm/qspinlock.h>
+#include <asm/qrwlock.h>
#endif /* _ASM_RISCV_SPINLOCK_H */
diff --git a/arch/riscv/include/asm/spinlock_types.h b/arch/riscv/include/asm/spinlock_types.h
index f398e7638dd6..d033a973f287 100644
--- a/arch/riscv/include/asm/spinlock_types.h
+++ b/arch/riscv/include/asm/spinlock_types.h
@@ -6,20 +6,11 @@
#ifndef _ASM_RISCV_SPINLOCK_TYPES_H
#define _ASM_RISCV_SPINLOCK_TYPES_H
-#ifndef __LINUX_SPINLOCK_TYPES_H
+#if !defined(__LINUX_SPINLOCK_TYPES_H) && !defined(_ASM_RISCV_SPINLOCK_H)
# error "please don't include this file directly"
#endif
-typedef struct {
- volatile unsigned int lock;
-} arch_spinlock_t;
-
-#define __ARCH_SPIN_LOCK_UNLOCKED { 0 }
-
-typedef struct {
- volatile unsigned int lock;
-} arch_rwlock_t;
-
-#define __ARCH_RW_LOCK_UNLOCKED { 0 }
+#include <asm-generic/qspinlock_types.h>
+#include <asm-generic/qrwlock_types.h>
#endif /* _ASM_RISCV_SPINLOCK_TYPES_H */
--
2.17.1
prev parent reply other threads:[~2021-03-27 18:08 UTC|newest]
Thread overview: 63+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-27 18:06 [PATCH v4 0/4] riscv: Add qspinlock/qrwlock guoren
2021-03-27 18:06 ` [PATCH v4 1/4] riscv: cmpxchg.h: Cleanup unused code guoren
2021-03-27 18:06 ` [PATCH v4 2/4] riscv: cmpxchg.h: Merge macros guoren
2021-03-27 21:25 ` Arnd Bergmann
2021-03-28 1:50 ` Guo Ren
2021-03-27 18:06 ` [PATCH v4 3/4] locking/qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32 guoren
2021-03-27 18:43 ` Waiman Long
2021-03-28 1:48 ` Guo Ren
2021-03-29 7:50 ` Peter Zijlstra
2021-03-29 9:41 ` Arnd Bergmann
2021-03-29 11:16 ` Peter Zijlstra
2021-03-29 11:29 ` Peter Zijlstra
2021-03-29 12:52 ` Guo Ren
2021-03-29 13:56 ` Arnd Bergmann
2021-03-30 2:26 ` Guo Ren
2021-03-30 5:51 ` Anup Patel
2021-03-30 6:26 ` Guo Ren
2021-03-30 7:11 ` Arnd Bergmann
2021-03-31 4:18 ` Guo Ren
2021-03-31 5:33 ` Paul Campbell
2021-04-05 16:12 ` Guo Ren
2021-03-31 6:44 ` Guo Ren
2021-03-31 7:12 ` Arnd Bergmann
2021-03-29 11:19 ` Guo Ren
2021-03-29 11:26 ` Peter Zijlstra
2021-03-29 12:01 ` Guo Ren
2021-03-29 12:49 ` Peter Zijlstra
2021-03-30 3:13 ` Guo Ren
2021-03-30 4:54 ` Anup Patel
2021-03-30 6:27 ` Guo Ren
2021-03-30 8:31 ` David Laight
2021-03-30 14:09 ` Waiman Long
2021-03-31 14:47 ` Guo Ren
2021-04-05 16:45 ` Guo Ren
2021-03-30 16:08 ` Peter Zijlstra
2021-03-30 22:35 ` Stafford Horne
2021-03-31 7:23 ` Arnd Bergmann
2021-03-31 12:31 ` Stafford Horne
2021-03-31 15:10 ` Guo Ren
2021-04-06 8:51 ` Stafford Horne
2021-04-06 3:50 ` Guo Ren
2021-04-06 8:56 ` Stafford Horne
2021-04-07 8:42 ` Arnd Bergmann
2021-04-07 11:36 ` Peter Zijlstra
2021-04-07 11:57 ` Arnd Bergmann
2021-04-07 12:02 ` Peter Zijlstra
2021-04-05 16:40 ` Guo Ren
2021-03-31 15:22 ` Guo Ren
2021-04-06 7:15 ` Peter Zijlstra
2021-04-07 9:42 ` Christoph Hellwig
2021-04-07 14:29 ` Christoph Müllner
2021-04-07 14:34 ` Christoph Hellwig
2021-04-07 15:51 ` Peter Zijlstra
2021-04-07 16:44 ` Peter Zijlstra
2021-04-07 15:52 ` Peter Zijlstra
2021-04-07 16:54 ` Peter Zijlstra
2021-04-07 16:00 ` Peter Zijlstra
2021-04-07 19:50 ` Christoph Müllner
2021-04-06 17:24 ` Boqun Feng
2021-04-07 9:26 ` Peter Zijlstra
2021-03-29 12:13 ` Anup Patel
2021-03-29 12:54 ` Peter Zijlstra
2021-03-27 18:06 ` guoren [this message]
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