From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: Greentime Hu <greentime.hu@sifive.com>, guoren@kernel.org
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Anup.Patel@wdc.com,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
linux-arch@vger.kernel.org, arnd@arndb.de,
linux-csky@vger.kernel.org,
linux-riscv <linux-riscv@lists.infradead.org>,
Guo Ren <guoren@linux.alibaba.com>,
Dave Martin <Dave.Martin@arm.com>
Subject: Re: [RFC PATCH V3 00/11] riscv: Add vector ISA support
Date: Mon, 9 Mar 2020 18:27:08 +0800 [thread overview]
Message-ID: <95e3bba4-65c0-8991-9523-c16977f6350f@c-sky.com> (raw)
In-Reply-To: <CAHCEeh+XYD3uVmaQRGpY=VGxpO9hzMeKasNmAojhkZe9PJ9Lug@mail.gmail.com>
On 2020/3/9 11:41, Greentime Hu wrote:
> On Sun, Mar 8, 2020 at 5:50 PM <guoren@kernel.org> wrote:
>> From: Guo Ren <guoren@linux.alibaba.com>
>>
>> The implementation follow the RISC-V "V" Vector Extension draft v0.8 with
>> 128bit-vlen and it's based on linux-5.6-rc3 and tested with qemu [1].
>>
>> The patch implement basic context switch, sigcontext save/restore and
>> ptrace interface with a new regset NT_RISCV_VECTOR. Only fixed 128bit-vlen
>> is implemented. We need to discuss about vlen-size for libc sigcontext and
>> ptrace (the maximum size of vlen is unlimited in spec).
>>
>> Puzzle:
>> Dave Martin has talked "Growing CPU register state without breaking ABI" [2]
>> before, and riscv also met vlen size problem. Let's discuss the common issue
>> for all architectures and we need a better solution for unlimited vlen.
>>
>> Any help are welcomed :)
>>
>> 1: https://github.com/romanheros/qemu.git branch:vector-upstream-v3
> Hi Guo,
>
> Thanks for your patch.
> It seems the qemu repo doesn't have this branch?
Hi Greentime,
It's a promise from me. Now it's ready. You can turn on vector by
"qemu-system-riscv64 -cpu rv64,v=true,vext_spec=v0.7.1".
Zhiwei
next prev parent reply other threads:[~2020-03-09 10:27 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-08 9:49 [RFC PATCH V3 00/11] riscv: Add vector ISA support guoren
2020-03-08 9:49 ` [RFC PATCH V3 01/11] riscv: Separate patch for cflags and aflags guoren
2020-03-08 9:49 ` [RFC PATCH V3 02/11] riscv: Rename __switch_to_aux -> fpu guoren
2020-03-08 9:49 ` [RFC PATCH V3 03/11] riscv: Extending cpufeature.c to detect V-extension guoren
2020-03-08 9:49 ` [RFC PATCH V3 04/11] riscv: Add CSR defines related to VECTOR extension guoren
2020-03-08 9:49 ` [RFC PATCH V3 05/11] riscv: Add vector feature to compile guoren
2020-03-08 9:49 ` [RFC PATCH V3 06/11] riscv: Add has_vector detect guoren
2020-03-08 9:49 ` [RFC PATCH V3 07/11] riscv: Reset vector register guoren
2020-03-08 9:49 ` [RFC PATCH V3 08/11] riscv: Add vector struct and assembler definitions guoren
2020-03-08 9:49 ` [RFC PATCH V3 09/11] riscv: Add task switch support for VECTOR guoren
2020-03-08 9:49 ` [RFC PATCH V3 10/11] riscv: Add ptrace support guoren
2020-03-08 9:49 ` [RFC PATCH V3 11/11] riscv: Add sigcontext save/restore guoren
2020-03-09 3:41 ` [RFC PATCH V3 00/11] riscv: Add vector ISA support Greentime Hu
2020-03-09 10:27 ` LIU Zhiwei [this message]
2020-03-10 8:54 ` Greentime Hu
2020-03-10 9:19 ` Greentime Hu
2020-03-12 3:14 ` LIU Zhiwei
2020-03-23 4:00 ` Greentime Hu
2020-03-24 3:41 ` Guo Ren
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