From: Ben Widawsky <ben.widawsky@intel.com>
To: linux-cxl@vger.kernel.org
Cc: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
linux-acpi@vger.kernel.org,
Dan Williams <dan.j.williams@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
"Kelley, Sean V" <sean.v.kelley@intel.com>,
Bjorn Helgaas <bhelgaas@google.com>,
"Rafael J . Wysocki" <rafael.j.wysocki@intel.com>,
Ben Widawsky <ben.widawsky@intel.com>
Subject: [RFC PATCH 7/9] cxl/mem: Implement polled mode mailbox
Date: Tue, 10 Nov 2020 21:43:54 -0800 [thread overview]
Message-ID: <20201111054356.793390-8-ben.widawsky@intel.com> (raw)
In-Reply-To: <20201111054356.793390-1-ben.widawsky@intel.com>
Create a function to handle sending a command, optionally with a
payload, to the memory device, polling on a result, and then optionally
copying out the payload. The algorithm for doing this come straight out
of the CXL 2.0 specification.
Primary mailboxes are capable of generating an interrupt when submitting
a command in the background. That implementation is saved for a later
time.
Secondary mailboxes aren't implemented at this time.
WARNING: This is untested with actual timeouts occurring.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
---
drivers/cxl/cxl.h | 16 +++++++
drivers/cxl/mem.c | 107 ++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 123 insertions(+)
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index 482fc9cdc890..f49ab80f68bd 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -21,8 +21,12 @@
#define CXLDEV_MB_CTRL 0x04
#define CXLDEV_MB_CTRL_DOORBELL BIT(0)
#define CXLDEV_MB_CMD 0x08
+#define CXLDEV_MB_CMD_PAYLOAD_LENGTH_SHIFT 16
#define CXLDEV_MB_STATUS 0x10
+#define CXLDEV_MB_STATUS_RET_CODE_SHIFT 32
+#define CXLDEV_MB_STATUS_RET_CODE_MASK 0xffff
#define CXLDEV_MB_BG_CMD_STATUS 0x18
+#define CXLDEV_MB_PAYLOAD 0x20
/* Memory Device */
#define CXLMDEV_STATUS 0
@@ -114,4 +118,16 @@ static inline u64 __cxl_raw_read_reg64(struct cxl_mem *cxlm, u32 reg)
return readq(reg_addr + reg);
}
+
+static inline void cxl_mbox_payload_fill(struct cxl_mem *cxlm, u8 *input,
+ unsigned int length)
+{
+ memcpy_toio(cxlm->mbox.regs + CXLDEV_MB_PAYLOAD, input, length);
+}
+
+static inline void cxl_mbox_payload_drain(struct cxl_mem *cxlm,
+ u8 *output, unsigned int length)
+{
+ memcpy_fromio(output, cxlm->mbox.regs + CXLDEV_MB_PAYLOAD, length);
+}
#endif /* __CXL_H__ */
diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c
index 9fd2d1daa534..08913360d500 100644
--- a/drivers/cxl/mem.c
+++ b/drivers/cxl/mem.c
@@ -1,5 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
// Copyright(c) 2020 Intel Corporation. All rights reserved.
+#include <linux/sched/clock.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/io.h>
@@ -7,6 +8,112 @@
#include "pci.h"
#include "cxl.h"
+struct mbox_cmd {
+ u16 cmd;
+ u8 *payload;
+ size_t payload_size;
+ u16 return_code;
+};
+
+static int cxldev_wait_for_doorbell(struct cxl_mem *cxlm)
+{
+ u64 start, now;
+ int cpu, ret, timeout = 2000000000;
+
+ start = local_clock();
+ preempt_disable();
+ cpu = smp_processor_id();
+ for (;;) {
+ now = local_clock();
+ preempt_enable();
+ if ((cxl_read_mbox_reg32(cxlm, CXLDEV_MB_CTRL) &
+ CXLDEV_MB_CTRL_DOORBELL) == 0) {
+ ret = 0;
+ break;
+ }
+
+ if (now - start >= timeout) {
+ ret = -ETIMEDOUT;
+ break;
+ }
+
+ cpu_relax();
+ preempt_disable();
+ if (unlikely(cpu != smp_processor_id())) {
+ timeout -= (now - start);
+ cpu = smp_processor_id();
+ start = local_clock();
+ }
+ }
+
+ return ret;
+}
+
+/*
+ * Returns 0 if the doorbell transaction was successful from a protocol level.
+ * Caller should check the return code in @mbox_cmd to make sure it succeeded.
+ */
+static int __maybe_unused cxl_mem_mbox_send_cmd(struct cxl_mem *cxlm, struct mbox_cmd *mbox_cmd)
+{
+ u64 cmd, status;
+ int rc;
+
+ lockdep_assert_held(&cxlm->mbox_lock);
+
+ /*
+ * Here are the steps from 8.2.8.4 of the CXL 2.0 spec.
+ * 1. Caller reads MB Control Register to verify doorbell is clear
+ * 2. Caller writes Command Register
+ * 3. Caller writes Command Payload Registers if input payload is non-empty
+ * 4. Caller writes MB Control Register to set doorbell
+ * 5. Caller either polls for doorbell to be clear or waits for interrupt if configured
+ * 6. Caller reads MB Status Register to fetch Return code
+ * 7. If command successful, Caller reads Command Register to get Payload Length
+ * 8. If output payload is non-empty, host reads Command Payload Registers
+ */
+
+ cmd = mbox_cmd->cmd;
+ if (mbox_cmd->payload_size) {
+ /* #3 */
+ cmd |= mbox_cmd->payload_size
+ << CXLDEV_MB_CMD_PAYLOAD_LENGTH_SHIFT;
+ cxl_mbox_payload_fill(cxlm, mbox_cmd->payload, mbox_cmd->payload_size);
+ }
+
+ /* #2 */
+ cxl_write_mbox_reg64(cxlm, CXLDEV_MB_CMD, cmd);
+
+ /* #4 */
+ cxl_write_mbox_reg32(cxlm, CXLDEV_MB_CTRL, CXLDEV_MB_CTRL_DOORBELL);
+
+ /* #5 */
+ rc = cxldev_wait_for_doorbell(cxlm);
+ if (rc == -ETIMEDOUT) {
+ dev_warn(&cxlm->pdev->dev, "Mailbox command timed out\n");
+ return rc;
+ }
+
+ /* #6 */
+ status = cxl_read_mbox_reg64(cxlm, CXLDEV_MB_STATUS);
+ cmd = cxl_read_mbox_reg64(cxlm, CXLDEV_MB_CMD);
+
+ mbox_cmd->return_code = (status >> CXLDEV_MB_STATUS_RET_CODE_SHIFT) &
+ CXLDEV_MB_STATUS_RET_CODE_MASK;
+
+ /* There was a problem, let the caller deal with it */
+ if (mbox_cmd->return_code != 0)
+ return 0;
+
+ /* #7 */
+ mbox_cmd->payload_size = cmd >> CXLDEV_MB_CMD_PAYLOAD_LENGTH_SHIFT;
+
+ /* #8 */
+ if (mbox_cmd->payload_size)
+ cxl_mbox_payload_drain(cxlm, mbox_cmd->payload, mbox_cmd->payload_size);
+
+ return 0;
+}
+
static int cxl_mem_mbox_get(struct cxl_mem *cxlm)
{
u64 md_status;
--
2.29.2
next prev parent reply other threads:[~2020-11-11 5:44 UTC|newest]
Thread overview: 67+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-11 5:43 [RFC PATCH 0/9] CXL 2.0 Support Ben Widawsky
2020-11-11 5:43 ` [RFC PATCH 1/9] cxl/acpi: Add an acpi_cxl module for the CXL interconnect Ben Widawsky
2020-11-11 6:17 ` Randy Dunlap
2020-11-11 7:10 ` Christoph Hellwig
2020-11-11 7:30 ` Verma, Vishal L
2020-11-11 7:34 ` hch
2020-11-11 7:36 ` Verma, Vishal L
2020-11-11 23:03 ` Bjorn Helgaas
2020-11-16 17:59 ` Jonathan Cameron
2020-11-16 18:23 ` Verma, Vishal L
2020-11-17 14:32 ` Rafael J. Wysocki
2020-11-17 21:45 ` Dan Williams
2020-11-18 11:14 ` Rafael J. Wysocki
2020-11-11 5:43 ` [RFC PATCH 2/9] cxl/acpi: add OSC support Ben Widawsky
2020-11-16 17:59 ` Jonathan Cameron
2020-11-16 23:25 ` Dan Williams
2020-11-18 12:25 ` Rafael J. Wysocki
2020-11-18 17:58 ` Dan Williams
2020-11-11 5:43 ` [RFC PATCH 3/9] cxl/mem: Add a driver for the type-3 mailbox Ben Widawsky
2020-11-11 6:17 ` Randy Dunlap
2020-11-11 7:12 ` Christoph Hellwig
2020-11-11 17:17 ` Dan Williams
2020-11-11 18:27 ` Dan Williams
2020-11-11 21:41 ` Randy Dunlap
2020-11-11 22:40 ` Dan Williams
2020-11-16 16:56 ` Christoph Hellwig
2020-11-13 18:17 ` Bjorn Helgaas
2020-11-14 1:08 ` Ben Widawsky
2020-11-15 0:23 ` Dan Williams
2020-11-17 14:49 ` Jonathan Cameron
2020-12-04 7:22 ` Dan Williams
2020-12-04 7:27 ` Dan Williams
2020-12-04 17:39 ` Jonathan Cameron
2020-11-11 5:43 ` [RFC PATCH 4/9] cxl/mem: Map memory device registers Ben Widawsky
2020-11-13 18:17 ` Bjorn Helgaas
2020-11-14 1:12 ` Ben Widawsky
2020-11-16 23:19 ` Dan Williams
2020-11-17 0:23 ` Bjorn Helgaas
2020-11-23 19:20 ` Ben Widawsky
2020-11-23 19:32 ` Dan Williams
2020-11-23 19:58 ` Ben Widawsky
2020-11-17 15:00 ` Jonathan Cameron
2020-11-11 5:43 ` [RFC PATCH 5/9] cxl/mem: Find device capabilities Ben Widawsky
2020-11-13 18:26 ` Bjorn Helgaas
2020-11-14 1:36 ` Ben Widawsky
2020-11-17 15:15 ` Jonathan Cameron
2020-11-24 0:17 ` Ben Widawsky
2020-11-26 6:05 ` Jon Masters
2020-11-26 18:18 ` Ben Widawsky
2020-12-04 7:35 ` Dan Williams
2020-12-04 7:41 ` Dan Williams
2020-12-07 6:12 ` Ben Widawsky
2020-11-11 5:43 ` [RFC PATCH 6/9] cxl/mem: Initialize the mailbox interface Ben Widawsky
2020-11-17 15:22 ` Jonathan Cameron
2020-11-11 5:43 ` Ben Widawsky [this message]
2020-11-13 23:14 ` [RFC PATCH 7/9] cxl/mem: Implement polled mode mailbox Bjorn Helgaas
2020-11-17 15:31 ` Jonathan Cameron
2020-11-17 16:34 ` Ben Widawsky
2020-11-17 18:06 ` Jonathan Cameron
2020-11-17 18:38 ` Dan Williams
2020-11-11 5:43 ` [RFC PATCH 8/9] cxl/mem: Register CXL memX devices Ben Widawsky
2020-11-17 15:56 ` Jonathan Cameron
2020-11-20 2:16 ` Dan Williams
2020-11-20 15:20 ` Jonathan Cameron
2020-11-11 5:43 ` [RFC PATCH 9/9] MAINTAINERS: Add maintainers of the CXL driver Ben Widawsky
2020-11-11 22:06 ` [RFC PATCH 0/9] CXL 2.0 Support Ben Widawsky
2020-11-11 22:43 ` Bjorn Helgaas
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