From: Ben Widawsky <ben.widawsky@intel.com>
To: linux-cxl@vger.kernel.org
Cc: Ben Widawsky <ben.widawsky@intel.com>,
Alison Schofield <alison.schofield@intel.com>,
Dan Williams <dan.j.williams@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
Jonathan Cameron <Jonathan.Cameron@Huawei.com>,
Vishal Verma <vishal.l.verma@intel.com>
Subject: [RFC PATCH 2/5] cxl/mem: Introduce CXL mem driver
Date: Thu, 17 Jun 2021 17:51:57 -0700 [thread overview]
Message-ID: <20210618005200.997804-3-ben.widawsky@intel.com> (raw)
In-Reply-To: <20210618005200.997804-1-ben.widawsky@intel.com>
CXL endpoints that participate in the CXL.mem protocol require extra
control to ensure architectural constraints are met for device
management.
This driver will implement those controls.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
---
drivers/cxl/Makefile | 3 ++-
drivers/cxl/core.c | 2 ++
drivers/cxl/cxl.h | 1 +
drivers/cxl/mem.c | 45 ++++++++++++++++++++++++++++++++++++++++++++
drivers/cxl/mem.h | 1 +
drivers/cxl/pci.c | 5 +++++
6 files changed, 56 insertions(+), 1 deletion(-)
create mode 100644 drivers/cxl/mem.c
diff --git a/drivers/cxl/Makefile b/drivers/cxl/Makefile
index f35077c073b8..1fc2836d4f12 100644
--- a/drivers/cxl/Makefile
+++ b/drivers/cxl/Makefile
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_CXL_BUS) += cxl_core.o
-obj-$(CONFIG_CXL_MEM) += cxl_pci.o cxl_region.o
+obj-$(CONFIG_CXL_MEM) += cxl_pci.o cxl_region.o mem.o
obj-$(CONFIG_CXL_ACPI) += cxl_acpi.o
obj-$(CONFIG_CXL_PMEM) += cxl_pmem.o
@@ -10,3 +10,4 @@ cxl_pci-y := pci.o
cxl_acpi-y := acpi.o
cxl_pmem-y := pmem.o
cxl_region-y := region.o
+cxl_mem-y := mem.o
diff --git a/drivers/cxl/core.c b/drivers/cxl/core.c
index 5d81fba787e9..16a671722d4e 100644
--- a/drivers/cxl/core.c
+++ b/drivers/cxl/core.c
@@ -1098,6 +1098,8 @@ static int cxl_device_id(struct device *dev)
return CXL_DEVICE_NVDIMM;
if (is_cxl_region(dev))
return CXL_DEVICE_REGION;
+ if (is_cxl_memdev(dev))
+ return CXL_DEVICE_ENDPOINT;
return 0;
}
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index b5b728155d86..ce4b241c5dda 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -328,6 +328,7 @@ void cxl_driver_unregister(struct cxl_driver *cxl_drv);
#define CXL_DEVICE_NVDIMM_BRIDGE 1
#define CXL_DEVICE_NVDIMM 2
#define CXL_DEVICE_REGION 3
+#define CXL_DEVICE_ENDPOINT 4
#define MODULE_ALIAS_CXL(type) MODULE_ALIAS("cxl:t" __stringify(type) "*")
#define CXL_MODALIAS_FMT "cxl:t%d"
diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c
new file mode 100644
index 000000000000..2997a03abcb6
--- /dev/null
+++ b/drivers/cxl/mem.c
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/* Copyright(c) 2021 Intel Corporation. All rights reserved. */
+#include <linux/device.h>
+#include <linux/module.h>
+#include "mem.h"
+
+/**
+ * DOC: cxl mem
+ *
+ * CXL memory endpoint devices are CXL capable devices that are participating in
+ * CXL.mem protocol. Their functionality builds on top of the CXL.io protocol
+ * that allows enumerating and configuring a CXL endpoint via standard PCI
+ * mechanisms.
+ */
+
+static int cxl_memdev_probe(struct device *dev)
+{
+ return -EOPNOTSUPP;
+}
+
+static void cxl_memdev_remove(struct device *dev)
+{
+}
+
+static struct cxl_driver cxl_memdev_driver = {
+ .name = "cxl_memdev",
+ .probe = cxl_memdev_probe,
+ .remove = cxl_memdev_remove,
+ .id = CXL_DEVICE_ENDPOINT,
+};
+
+static __init int cxl_memdev_init(void)
+{
+ return cxl_driver_register(&cxl_memdev_driver);
+}
+
+static __exit void cxl_memdev_exit(void)
+{
+ cxl_driver_unregister(&cxl_memdev_driver);
+}
+
+MODULE_LICENSE("GPL v2");
+module_init(cxl_memdev_init);
+module_exit(cxl_memdev_exit);
+MODULE_IMPORT_NS(CXL);
diff --git a/drivers/cxl/mem.h b/drivers/cxl/mem.h
index 3d51bf6c090f..2c20c1ccd6b8 100644
--- a/drivers/cxl/mem.h
+++ b/drivers/cxl/mem.h
@@ -88,5 +88,6 @@ static inline bool is_cxl_capable(struct cxl_memdev *cxlmd)
{
return false;
}
+bool is_cxl_memdev(struct device *dev);
#endif /* __CXL_MEM_H__ */
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
index 379a106ada94..f9c0eaf3ff4e 100644
--- a/drivers/cxl/pci.c
+++ b/drivers/cxl/pci.c
@@ -1276,6 +1276,11 @@ static const struct device_type cxl_memdev_type = {
.groups = cxl_memdev_attribute_groups,
};
+bool is_cxl_memdev(struct device *dev)
+{
+ return dev->type == &cxl_memdev_type;
+}
+
static void cxl_memdev_shutdown(struct cxl_memdev *cxlmd)
{
down_write(&cxl_memdev_rwsem);
--
2.32.0
next prev parent reply other threads:[~2021-06-18 0:52 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-18 0:51 [RFC PATCH 0/5] Introduce memdev driver Ben Widawsky
2021-06-18 0:51 ` [RFC PATCH 1/5] cxl/region: Only allow CXL capable targets Ben Widawsky
2021-06-18 14:08 ` Jonathan Cameron
2021-06-18 0:51 ` Ben Widawsky [this message]
2021-06-18 0:51 ` [RFC PATCH 3/5] cxl/memdev: Determine CXL.mem capability Ben Widawsky
2021-06-18 14:14 ` Jonathan Cameron
2021-06-18 0:51 ` [RFC PATCH 4/5] cxl/pci: Export CXL DVSEC functionality Ben Widawsky
2021-06-18 15:00 ` Dan Williams
2021-06-18 0:52 ` [RFC PATCH 5/5] cxl/mem: Check that the device is CXL.mem capable Ben Widawsky
2021-06-18 14:24 ` Jonathan Cameron
2021-06-18 14:27 ` [RFC PATCH 0/5] Introduce memdev driver Jonathan Cameron
2021-06-30 17:49 ` Dan Williams
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210618005200.997804-3-ben.widawsky@intel.com \
--to=ben.widawsky@intel.com \
--cc=Jonathan.Cameron@Huawei.com \
--cc=alison.schofield@intel.com \
--cc=dan.j.williams@intel.com \
--cc=ira.weiny@intel.com \
--cc=linux-cxl@vger.kernel.org \
--cc=vishal.l.verma@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).