From: Ben Widawsky <ben.widawsky@intel.com>
To: linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org
Cc: Ben Widawsky <ben.widawsky@intel.com>,
Alison Schofield <alison.schofield@intel.com>,
Dan Williams <dan.j.williams@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
Jonathan Cameron <Jonathan.Cameron@Huawei.com>,
Vishal Verma <vishal.l.verma@intel.com>
Subject: [PATCH 03/23] cxl/pci: Extract device status check
Date: Fri, 19 Nov 2021 16:02:30 -0800 [thread overview]
Message-ID: <20211120000250.1663391-4-ben.widawsky@intel.com> (raw)
In-Reply-To: <20211120000250.1663391-1-ben.widawsky@intel.com>
The Memory Device Status register is inspected in the same way for at
least two flows in the CXL Type 3 Memory Device Software Guide
(Revision: 1.0): 2.13.9 Device discovery and mailbox ready sequence,
and 2.13.10 Media ready sequence. Extract this common functionality for
use by both.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
---
This patch did not exist in RFCv2
---
drivers/cxl/pci.c | 33 +++++++++++++++++++++++++--------
1 file changed, 25 insertions(+), 8 deletions(-)
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
index a6ea9811a05b..6c8d09fb3a17 100644
--- a/drivers/cxl/pci.c
+++ b/drivers/cxl/pci.c
@@ -182,6 +182,27 @@ static int __cxl_pci_mbox_send_cmd(struct cxl_dev_state *cxlds,
return 0;
}
+/*
+ * Implements roughly the bottom half of Figure 42 of the CXL Type 3 Memory
+ * Device Software Guide
+ */
+static int check_device_status(struct cxl_dev_state *cxlds)
+{
+ const u64 md_status = readq(cxlds->regs.memdev + CXLMDEV_STATUS_OFFSET);
+
+ if (md_status & CXLMDEV_DEV_FATAL) {
+ dev_err(cxlds->dev, "Fatal: replace device\n");
+ return -EIO;
+ }
+
+ if (md_status & CXLMDEV_FW_HALT) {
+ dev_err(cxlds->dev, "FWHalt: reset or replace device\n");
+ return -EBUSY;
+ }
+
+ return 0;
+}
+
/**
* cxl_pci_mbox_get() - Acquire exclusive access to the mailbox.
* @cxlds: The device state to gain access to.
@@ -231,17 +252,13 @@ static int cxl_pci_mbox_get(struct cxl_dev_state *cxlds)
* Hardware shouldn't allow a ready status but also have failure bits
* set. Spit out an error, this should be a bug report
*/
- rc = -EFAULT;
- if (md_status & CXLMDEV_DEV_FATAL) {
- dev_err(dev, "mbox: reported ready, but fatal\n");
+ rc = check_device_status(cxlds);
+ if (rc)
goto out;
- }
- if (md_status & CXLMDEV_FW_HALT) {
- dev_err(dev, "mbox: reported ready, but halted\n");
- goto out;
- }
+
if (CXLMDEV_RESET_NEEDED(md_status)) {
dev_err(dev, "mbox: reported ready, but reset needed\n");
+ rc = -EFAULT;
goto out;
}
--
2.34.0
next prev parent reply other threads:[~2021-11-20 0:03 UTC|newest]
Thread overview: 127+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-20 0:02 [PATCH 00/23] Add drivers for CXL ports and mem devices Ben Widawsky
2021-11-20 0:02 ` [PATCH 01/23] cxl: Rename CXL_MEM to CXL_PCI Ben Widawsky
2021-11-22 14:47 ` Jonathan Cameron
2021-11-24 4:15 ` Dan Williams
2021-11-20 0:02 ` [PATCH 02/23] cxl: Flesh out register names Ben Widawsky
2021-11-22 14:49 ` Jonathan Cameron
2021-11-24 4:24 ` Dan Williams
2021-11-20 0:02 ` Ben Widawsky [this message]
2021-11-22 15:03 ` [PATCH 03/23] cxl/pci: Extract device status check Jonathan Cameron
2021-11-24 19:30 ` Dan Williams
2021-11-20 0:02 ` [PATCH 04/23] cxl/pci: Implement Interface Ready Timeout Ben Widawsky
2021-11-22 15:02 ` Jonathan Cameron
2021-11-22 17:17 ` Ben Widawsky
2021-11-22 17:53 ` Jonathan Cameron
2021-11-24 19:56 ` Dan Williams
2021-11-25 6:17 ` Ben Widawsky
2021-11-25 7:14 ` Dan Williams
2021-11-20 0:02 ` [PATCH 05/23] cxl/pci: Don't poll doorbell for mailbox access Ben Widawsky
2021-11-22 15:11 ` Jonathan Cameron
2021-11-22 17:24 ` Ben Widawsky
2021-11-24 21:55 ` Dan Williams
2021-11-29 18:33 ` Ben Widawsky
2021-11-29 19:02 ` Dan Williams
2021-11-29 19:11 ` Ben Widawsky
2021-11-29 19:18 ` Dan Williams
2021-11-29 19:31 ` Ben Widawsky
2021-11-29 19:37 ` Dan Williams
2021-11-29 19:50 ` Ben Widawsky
2021-11-20 0:02 ` [PATCH 06/23] cxl/pci: Don't check media status for mbox access Ben Widawsky
2021-11-22 15:19 ` Jonathan Cameron
2021-11-24 21:58 ` Dan Williams
2021-11-20 0:02 ` [PATCH 07/23] cxl/pci: Add new DVSEC definitions Ben Widawsky
2021-11-22 15:22 ` Jonathan Cameron
2021-11-22 17:32 ` Ben Widawsky
2021-11-24 22:03 ` Dan Williams
2021-11-20 0:02 ` [PATCH 08/23] cxl/acpi: Map component registers for Root Ports Ben Widawsky
2021-11-22 15:51 ` Jonathan Cameron
2021-11-22 19:28 ` Ben Widawsky
2021-11-24 22:18 ` Dan Williams
2021-11-20 0:02 ` [PATCH 09/23] cxl: Introduce module_cxl_driver Ben Widawsky
2021-11-22 15:54 ` Jonathan Cameron
2021-11-24 22:22 ` Dan Williams
2021-11-20 0:02 ` [PATCH 10/23] cxl/core: Convert decoder range to resource Ben Widawsky
2021-11-22 16:08 ` Jonathan Cameron
2021-11-24 22:41 ` Dan Williams
2021-11-20 0:02 ` [PATCH 11/23] cxl/core: Document and tighten up decoder APIs Ben Widawsky
2021-11-22 16:13 ` Jonathan Cameron
2021-11-24 22:55 ` Dan Williams
2021-11-20 0:02 ` [PATCH 12/23] cxl: Introduce endpoint decoders Ben Widawsky
2021-11-22 16:20 ` Jonathan Cameron
2021-11-22 19:37 ` Ben Widawsky
2021-11-25 0:07 ` Dan Williams
2021-11-29 20:05 ` Ben Widawsky
2021-11-29 20:07 ` Dan Williams
2021-11-29 20:12 ` Ben Widawsky
2021-11-20 0:02 ` [PATCH 13/23] cxl/core: Move target population locking to caller Ben Widawsky
2021-11-22 16:33 ` Jonathan Cameron
2021-11-22 21:58 ` Ben Widawsky
2021-11-23 11:05 ` Jonathan Cameron
2021-11-25 0:34 ` Dan Williams
2021-11-20 0:02 ` [PATCH 14/23] cxl: Introduce topology host registration Ben Widawsky
2021-11-22 18:20 ` Jonathan Cameron
2021-11-22 22:30 ` Ben Widawsky
2021-11-25 1:09 ` Dan Williams
2021-11-29 21:23 ` Ben Widawsky
2021-11-29 11:42 ` Dan Carpenter
2021-11-20 0:02 ` [PATCH 15/23] cxl/core: Store global list of root ports Ben Widawsky
2021-11-22 18:22 ` Jonathan Cameron
2021-11-22 22:32 ` Ben Widawsky
2021-11-20 0:02 ` [PATCH 16/23] cxl/pci: Cache device DVSEC offset Ben Widawsky
2021-11-22 16:46 ` Jonathan Cameron
2021-11-22 22:34 ` Ben Widawsky
2021-11-20 0:02 ` [PATCH 17/23] cxl: Cache and pass DVSEC ranges Ben Widawsky
2021-11-20 4:29 ` kernel test robot
2021-11-22 17:00 ` Jonathan Cameron
2021-11-22 22:50 ` Ben Widawsky
2021-11-26 11:37 ` Jonathan Cameron
2021-11-20 0:02 ` [PATCH 18/23] cxl/pci: Implement wait for media active Ben Widawsky
2021-11-22 17:03 ` Jonathan Cameron
2021-11-22 22:57 ` Ben Widawsky
2021-11-23 11:09 ` Jonathan Cameron
2021-11-23 16:04 ` Ben Widawsky
2021-11-23 17:48 ` Bjorn Helgaas
2021-11-23 19:37 ` Ben Widawsky
2021-11-26 11:36 ` Jonathan Cameron
2021-11-20 0:02 ` [PATCH 19/23] cxl/pci: Store component register base in cxlds Ben Widawsky
2021-11-20 7:28 ` kernel test robot
2021-11-22 17:11 ` Jonathan Cameron
2021-11-22 23:01 ` Ben Widawsky
2021-11-20 0:02 ` [PATCH 20/23] cxl/port: Introduce a port driver Ben Widawsky
2021-11-20 3:14 ` kernel test robot
2021-11-20 5:38 ` kernel test robot
2021-11-22 17:41 ` Jonathan Cameron
2021-11-22 23:38 ` Ben Widawsky
2021-11-23 11:38 ` Jonathan Cameron
2021-11-23 16:14 ` Ben Widawsky
2021-11-23 18:21 ` Bjorn Helgaas
2021-11-23 22:03 ` Ben Widawsky
2021-11-23 22:36 ` Dan Williams
2021-11-23 23:38 ` Ben Widawsky
2021-11-23 23:55 ` Bjorn Helgaas
2021-11-24 0:40 ` Dan Williams
2021-11-24 6:33 ` Christoph Hellwig
2021-11-24 7:17 ` Dan Williams
2021-11-24 7:28 ` Christoph Hellwig
2021-11-24 7:33 ` Greg Kroah-Hartman
2021-11-24 7:54 ` Dan Williams
2021-11-24 8:21 ` Greg Kroah-Hartman
2021-11-24 18:24 ` Dan Williams
2021-12-02 21:24 ` Bjorn Helgaas
2021-12-03 1:38 ` Dan Williams
2021-12-03 22:03 ` Bjorn Helgaas
2021-12-04 1:24 ` Dan Williams
2021-12-07 2:56 ` Bjorn Helgaas
2021-12-07 4:48 ` Dan Williams
2021-11-24 21:31 ` Bjorn Helgaas
2021-11-20 0:02 ` [PATCH 21/23] cxl: Unify port enumeration for decoders Ben Widawsky
2021-11-22 17:48 ` Jonathan Cameron
2021-11-22 23:44 ` Ben Widawsky
2021-11-20 0:02 ` [PATCH 22/23] cxl/mem: Introduce cxl_mem driver Ben Widawsky
2021-11-20 0:40 ` Randy Dunlap
2021-11-21 3:55 ` Ben Widawsky
2021-11-22 18:17 ` Jonathan Cameron
2021-11-23 0:05 ` Ben Widawsky
2021-11-20 0:02 ` [PATCH 23/23] cxl/mem: Disable switch hierarchies for now Ben Widawsky
2021-11-22 18:19 ` Jonathan Cameron
2021-11-22 19:17 ` Ben Widawsky
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