From: Mark Rutland <mark.rutland@arm.com>
To: Ard Biesheuvel <ardb@kernel.org>
Cc: devicetree@vger.kernel.org,
Brijesh Singh <brijeshkumar.singh@amd.com>,
Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>,
Tom Lendacky <thomas.lendacky@amd.com>,
Rob Herring <robh+dt@kernel.org>
Subject: Re: [PATCH v2 8/8] dt: amd-seattle: add a description of the CPUs and caches
Date: Tue, 26 Nov 2019 11:59:45 +0000 [thread overview]
Message-ID: <20191126115944.GB32965@lakrids.cambridge.arm.com> (raw)
In-Reply-To: <20191126114319.2755-9-ardb@kernel.org>
On Tue, Nov 26, 2019 at 12:43:19PM +0100, Ard Biesheuvel wrote:
> Add a DT description of the CPU and cache hierarchy as found on
> the AMD Seattle SOC. Given the tight coupling of the PMU with
> the CPUs, move the PMU node into the cpu .dtsi file as well, and
> add the missing affinity description.
[...]
> + CPU0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,armv8";
This should be "arm,cortex-a57"; likewise for the other CPUs.
> + pmu {
> + compatible = "arm,armv8-pmuv3";
And this should be (and should have been) "arm,cortex-a57-pmu".
> + interrupts = <0x0 0x7 0x4>,
> + <0x0 0x8 0x4>,
> + <0x0 0x9 0x4>,
> + <0x0 0xa 0x4>,
> + <0x0 0xb 0x4>,
> + <0x0 0xc 0x4>,
> + <0x0 0xd 0x4>,
> + <0x0 0xe 0x4>;
> + interrupt-affinity = <&CPU0>,
> + <&CPU1>,
> + <&CPU2>,
> + <&CPU3>,
> + <&CPU4>,
> + <&CPU5>,
> + <&CPU6>,
> + <&CPU7>;
> + };
> +};
Otherwise, this looks good to me.
Thanks,
Mark.
prev parent reply other threads:[~2019-11-26 11:59 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-26 11:43 [PATCH v2 0/8] dt: amd-seattle: update SMMU, PCIe and cache descriptions Ard Biesheuvel
2019-11-26 11:43 ` [PATCH v2 1/8] dt: amd-seattle: remove Husky platform Ard Biesheuvel
2019-11-26 11:43 ` [PATCH v2 2/8] dt: amd-seattle: remove Overdrive revision A0 support Ard Biesheuvel
2019-11-26 11:43 ` [PATCH v2 3/8] dt: amd-seattle: upgrade AMD Seattle XGBE to new SMMU binding Ard Biesheuvel
2019-11-26 11:43 ` [PATCH v2 4/8] dt: amd-seattle: fix PCIe legacy interrupt routing Ard Biesheuvel
2019-11-26 11:43 ` [PATCH v2 5/8] dt: amd-seattle: add a description of the PCIe SMMU Ard Biesheuvel
2019-11-26 11:43 ` [PATCH v2 6/8] dt: amd-seattle: add description of the SATA/CCP SMMUs Ard Biesheuvel
2019-12-03 14:10 ` Ard Biesheuvel
2019-12-03 14:33 ` Rob Herring
2019-11-26 11:43 ` [PATCH v2 7/8] dt: amd-seattle: disable IPMI controller and some GPIO blocks on B0 Ard Biesheuvel
2019-11-26 11:43 ` [PATCH v2 8/8] dt: amd-seattle: add a description of the CPUs and caches Ard Biesheuvel
2019-11-26 11:59 ` Mark Rutland [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20191126115944.GB32965@lakrids.cambridge.arm.com \
--to=mark.rutland@arm.com \
--cc=ardb@kernel.org \
--cc=brijeshkumar.singh@amd.com \
--cc=devicetree@vger.kernel.org \
--cc=robh+dt@kernel.org \
--cc=suravee.suthikulpanit@amd.com \
--cc=thomas.lendacky@amd.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).