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[68.147.8.254]) by smtp.gmail.com with ESMTPSA id c6sm17762524pfj.59.2019.11.27.10.18.24 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 27 Nov 2019 10:18:25 -0800 (PST) Date: Wed, 27 Nov 2019 11:18:23 -0700 From: Mathieu Poirier To: Mike Leach Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, suzuki.poulose@arm.com Subject: Re: [PATCH v5 10/14] dt-bindings: qcom: Add CTI options for qcom msm8916 Message-ID: <20191127181823.GB26544@xps15> References: <20191119231912.12768-1-mike.leach@linaro.org> <20191119231912.12768-11-mike.leach@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20191119231912.12768-11-mike.leach@linaro.org> User-Agent: Mutt/1.9.4 (2018-02-28) Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Tue, Nov 19, 2019 at 11:19:08PM +0000, Mike Leach wrote: > Adds system and CPU bound CTI definitions for Qualcom msm8916 platform > (Dragonboard DB410C). > System CTIs 2-11 are omitted as no information available at present. > > Signed-off-by: Mike Leach > --- > arch/arm64/boot/dts/qcom/msm8916.dtsi | 85 +++++++++++++++++++++++++-- > 1 file changed, 81 insertions(+), 4 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi > index 5ea9fb8f2f87..9589fc2cba22 100644 > --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi > +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi > @@ -8,6 +8,7 @@ > #include > #include > #include > +#include > > / { > interrupt-parent = <&intc>; > @@ -1357,7 +1358,7 @@ > cpu = <&CPU3>; > }; > > - etm@85c000 { > + etm0: etm@85c000 { > compatible = "arm,coresight-etm4x", "arm,primecell"; > reg = <0x85c000 0x1000>; > > @@ -1375,7 +1376,7 @@ > }; > }; > > - etm@85d000 { > + etm1: etm@85d000 { > compatible = "arm,coresight-etm4x", "arm,primecell"; > reg = <0x85d000 0x1000>; > > @@ -1393,7 +1394,7 @@ > }; > }; > > - etm@85e000 { > + etm2: etm@85e000 { > compatible = "arm,coresight-etm4x", "arm,primecell"; > reg = <0x85e000 0x1000>; > > @@ -1411,7 +1412,7 @@ > }; > }; > > - etm@85f000 { > + etm3: etm@85f000 { > compatible = "arm,coresight-etm4x", "arm,primecell"; > reg = <0x85f000 0x1000>; > > @@ -1429,6 +1430,82 @@ > }; > }; > > + /* System CTIs */ > + /* CTI 0 - TMC connections */ > + cti@810000 { > + compatible = "arm,coresight-cti", "arm,primecell"; > + reg = <0x810000 0x1000>; > + > + clocks = <&rpmcc RPM_QDSS_CLK>; > + clock-names = "apb_pclk"; > + }; > + > + /* CTI 1 - TPIU connections */ > + cti@811000 { > + compatible = "arm,coresight-cti", "arm,primecell"; > + reg = <0x811000 0x1000>; > + > + clocks = <&rpmcc RPM_QDSS_CLK>; > + clock-names = "apb_pclk"; > + }; > + > + /* CTIs 2-11 - no information - not instantiated */ > + > + /* Core CTIs; CTIs 12-15 */ > + /* CTI - CPU-0 */ > + cti@858000 { > + compatible = "arm,coresight-cti", "arm,primecell"; > + reg = <0x858000 0x1000>; > + > + clocks = <&rpmcc RPM_QDSS_CLK>; > + clock-names = "apb_pclk"; > + > + arm,cti-v8-arch; > + cpu = <&CPU0>; > + arm,cs-dev-assoc = <&etm0>; > + > + }; > + > + /* CTI - CPU-1 */ > + cti@859000 { > + compatible = "arm,coresight-cti", "arm,primecell"; > + reg = <0x859000 0x1000>; > + > + clocks = <&rpmcc RPM_QDSS_CLK>; > + clock-names = "apb_pclk"; > + > + arm,cti-v8-arch; > + cpu = <&CPU1>; > + arm,cs-dev-assoc = <&etm1>; > + }; > + > + /* CTI - CPU-2 */ > + cti@85a000 { > + compatible = "arm,coresight-cti", "arm,primecell"; > + reg = <0x85a000 0x1000>; > + > + clocks = <&rpmcc RPM_QDSS_CLK>; > + clock-names = "apb_pclk"; > + > + arm,cti-v8-arch; > + cpu = <&CPU2>; > + arm,cs-dev-assoc = <&etm2>; > + }; > + > + /* CTI - CPU-3 */ > + cti@85b000 { > + compatible = "arm,coresight-cti", "arm,primecell"; > + reg = <0x85b000 0x1000>; > + > + clocks = <&rpmcc RPM_QDSS_CLK>; > + clock-names = "apb_pclk"; > + > + arm,cti-v8-arch; > + cpu = <&CPU3>; > + arm,cs-dev-assoc = <&etm3>; > + }; > + > + This looks good to me. Since Andy Gross maintains this file you will have to CC him on your next revision. Right now chances are he hasn't see it. > venus: video-codec@1d00000 { > compatible = "qcom,msm8916-venus"; > reg = <0x01d00000 0xff000>; > -- > 2.17.1 >