From: Vinod Koul <vkoul@kernel.org>
To: Peter Ujfalusi <peter.ujfalusi@ti.com>
Cc: robh+dt@kernel.org, nm@ti.com, ssantosh@kernel.org,
dan.j.williams@intel.com, dmaengine@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, grygorii.strashko@ti.com,
lokeshvutla@ti.com, t-kristo@ti.com, tony@atomide.com,
j-keerthy@ti.com, vigneshr@ti.com
Subject: Re: [PATCH v7 09/12] dmaengine: ti: New driver for K3 UDMA
Date: Mon, 23 Dec 2019 16:56:23 +0530 [thread overview]
Message-ID: <20191223112623.GF2536@vkoul-mobl> (raw)
In-Reply-To: <ea473fed-276f-6b71-070b-02ab1f51ed89@ti.com>
On 23-12-19, 10:59, Peter Ujfalusi wrote:
> >> +static void udma_reset_counters(struct udma_chan *uc)
> >> +{
> >> + u32 val;
> >> +
> >> + if (uc->tchan) {
> >> + val = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_BCNT_REG);
> >> + udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_BCNT_REG, val);
> >
> > so you read back from UDMA_TCHAN_RT_BCNT_REG and write same value to
> > it??
>
> Yes, that's correct. This is how we can reset it. The counter is
> decremented with the value you have written to the register.
aha, with so many read+write back I would have added a helper.. Not a
big deal though can be updated later
> >> +static struct udma_desc *udma_alloc_tr_desc(struct udma_chan *uc,
> >> + size_t tr_size, int tr_count,
> >> + enum dma_transfer_direction dir)
> >> +{
> >> + struct udma_hwdesc *hwdesc;
> >> + struct cppi5_desc_hdr_t *tr_desc;
> >> + struct udma_desc *d;
> >> + u32 reload_count = 0;
> >> + u32 ring_id;
> >> +
> >> + switch (tr_size) {
> >> + case 16:
> >> + case 32:
> >> + case 64:
> >> + case 128:
> >> + break;
> >> + default:
> >> + dev_err(uc->ud->dev, "Unsupported TR size of %zu\n", tr_size);
> >> + return NULL;
> >> + }
> >> +
> >> + /* We have only one descriptor containing multiple TRs */
> >> + d = kzalloc(sizeof(*d) + sizeof(d->hwdesc[0]), GFP_ATOMIC);
> >
> > this is invoked from prep_ so should use GFP_NOWAIT, we dont use
> > GFP_ATOMIC :)
>
> Ok. btw: EDMA and sDMA driver is using GFP_ATOMIC :o
heh, we made sure to document this bit :)
> >> +static int udma_configure_statictr(struct udma_chan *uc, struct udma_desc *d,
> >> + enum dma_slave_buswidth dev_width,
> >> + u16 elcnt)
> >> +{
> >> + if (uc->ep_type != PSIL_EP_PDMA_XY)
> >> + return 0;
> >> +
> >> + /* Bus width translates to the element size (ES) */
> >> + switch (dev_width) {
> >> + case DMA_SLAVE_BUSWIDTH_1_BYTE:
> >> + d->static_tr.elsize = 0;
> >> + break;
> >> + case DMA_SLAVE_BUSWIDTH_2_BYTES:
> >> + d->static_tr.elsize = 1;
> >> + break;
> >> + case DMA_SLAVE_BUSWIDTH_3_BYTES:
> >> + d->static_tr.elsize = 2;
> >> + break;
> >> + case DMA_SLAVE_BUSWIDTH_4_BYTES:
> >> + d->static_tr.elsize = 3;
> >> + break;
> >> + case DMA_SLAVE_BUSWIDTH_8_BYTES:
> >> + d->static_tr.elsize = 4;
> >
> > seems like ffs(dev_width) to me?
>
> Not really:
> ffs(DMA_SLAVE_BUSWIDTH_1_BYTE) = 1
> ffs(DMA_SLAVE_BUSWIDTH_2_BYTES) = 2
> ffs(DMA_SLAVE_BUSWIDTH_3_BYTES) = 1
I missed this!
> ffs(DMA_SLAVE_BUSWIDTH_4_BYTES) = 3
> ffs(DMA_SLAVE_BUSWIDTH_8_BYTES) = 4
Otherwise you are ffs() - 1
--
~Vinod
next prev parent reply other threads:[~2019-12-23 11:26 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-09 9:43 [PATCH v7 00/12] dmaengine/soc: Add Texas Instruments UDMA support Peter Ujfalusi
2019-12-09 9:43 ` [PATCH v7 01/12] bindings: soc: ti: add documentation for k3 ringacc Peter Ujfalusi
2019-12-09 9:43 ` [PATCH v7 02/12] soc: ti: k3: add navss ringacc driver Peter Ujfalusi
2019-12-09 9:43 ` [PATCH v7 03/12] dmaengine: doc: Add sections for per descriptor metadata support Peter Ujfalusi
2019-12-20 8:28 ` Vinod Koul
2019-12-20 9:52 ` Peter Ujfalusi
2019-12-20 10:14 ` Vinod Koul
2019-12-09 9:43 ` [PATCH v7 04/12] dmaengine: Add metadata_ops for dma_async_tx_descriptor Peter Ujfalusi
2019-12-20 8:32 ` Vinod Koul
2019-12-20 8:48 ` Peter Ujfalusi
2019-12-09 9:43 ` [PATCH v7 05/12] dmaengine: Add support for reporting DMA cached data amount Peter Ujfalusi
2019-12-20 8:37 ` Vinod Koul
2019-12-20 8:49 ` Peter Ujfalusi
2019-12-20 9:57 ` Vinod Koul
2019-12-20 10:13 ` Peter Ujfalusi
2019-12-09 9:43 ` [PATCH v7 06/12] dmaengine: ti: Add cppi5 header for K3 NAVSS/UDMA Peter Ujfalusi
2019-12-20 9:54 ` Vinod Koul
2019-12-20 10:42 ` Peter Ujfalusi
2019-12-23 7:11 ` Peter Ujfalusi
2019-12-09 9:43 ` [PATCH v7 07/12] dmaengine: ti: k3 PSI-L remote endpoint configuration Peter Ujfalusi
2019-12-09 9:43 ` [PATCH v7 08/12] dt-bindings: dma: ti: Add document for K3 UDMA Peter Ujfalusi
2019-12-23 6:53 ` Vinod Koul
2019-12-09 9:43 ` [PATCH v7 09/12] dmaengine: ti: New driver " Peter Ujfalusi
2019-12-23 7:34 ` Vinod Koul
2019-12-23 8:59 ` Peter Ujfalusi
2019-12-23 11:26 ` Vinod Koul [this message]
2019-12-09 9:43 ` [PATCH v7 10/12] dmaengine: ti: k3-udma: Add glue layer for non DMAengine users Peter Ujfalusi
2019-12-09 9:43 ` [PATCH v7 11/12] firmware: ti_sci: rm: Add support for tx_tdtype parameter for tx channel Peter Ujfalusi
2019-12-11 10:24 ` Tero Kristo
2019-12-09 9:43 ` [PATCH v7 12/12] dmaengine: ti: k3-udma: Wait for peer teardown completion if supported Peter Ujfalusi
2019-12-11 10:43 ` [PATCH v7 00/12] dmaengine/soc: Add Texas Instruments UDMA support Keerthy
2019-12-12 8:46 ` Peter Ujfalusi
2019-12-12 10:55 ` Tero Kristo
2019-12-12 10:57 ` Tero Kristo
2019-12-16 10:05 ` Peter Ujfalusi
2019-12-12 18:01 ` Grygorii Strashko
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