From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6B28BC433E2 for ; Sat, 20 Jun 2020 14:43:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4C55D23BDD for ; Sat, 20 Jun 2020 14:43:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728217AbgFTOnh (ORCPT ); Sat, 20 Jun 2020 10:43:37 -0400 Received: from vps0.lunn.ch ([185.16.172.187]:50052 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728214AbgFTOnh (ORCPT ); Sat, 20 Jun 2020 10:43:37 -0400 Received: from andrew by vps0.lunn.ch with local (Exim 4.94) (envelope-from ) id 1jmeiH-001PCT-CW; Sat, 20 Jun 2020 16:43:21 +0200 Date: Sat, 20 Jun 2020 16:43:21 +0200 From: Andrew Lunn To: Oleksij Rempel Cc: Geert Uytterhoeven , Sergei Shtylyov , "David S . Miller" , Jakub Kicinski , Rob Herring , Philippe Schenker , Florian Fainelli , Heiner Kallweit , Kazuya Mizuguchi , Wolfram Sang , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org Subject: Re: [PATCH/RFC 1/5] dt-bindings: net: renesas,ravb: Document internal clock delay properties Message-ID: <20200620144321.GH304147@lunn.ch> References: <20200619191554.24942-1-geert+renesas@glider.be> <20200619191554.24942-2-geert+renesas@glider.be> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Sat, Jun 20, 2020 at 07:47:16AM +0200, Oleksij Rempel wrote: > Hi Geert, > > Am 19.06.20 um 21:15 schrieb Geert Uytterhoeven: > > Some EtherAVB variants support internal clock delay configuration, which > > can add larger delays than the delays that are typically supported by > > the PHY (using an "rgmii-*id" PHY mode, and/or "[rt]xc-skew-ps" > > properties). > > > > Add properties for configuring the internal MAC delays. > > These properties are mandatory, even when specified as zero, to > > distinguish between old and new DTBs. > > > > Update the example accordingly. > > > > Signed-off-by: Geert Uytterhoeven > > --- > > .../devicetree/bindings/net/renesas,ravb.txt | 29 ++++++++++--------- > > 1 file changed, 16 insertions(+), 13 deletions(-) > > > > diff --git a/Documentation/devicetree/bindings/net/renesas,ravb.txt b/Documentation/devicetree/bindings/net/renesas,ravb.txt > > index 032b76f14f4fdb38..488ada78b6169b8e 100644 > > --- a/Documentation/devicetree/bindings/net/renesas,ravb.txt > > +++ b/Documentation/devicetree/bindings/net/renesas,ravb.txt > > @@ -64,6 +64,18 @@ Optional properties: > > AVB_LINK signal. > > - renesas,ether-link-active-low: boolean, specify when the AVB_LINK signal is > > active-low instead of normal active-high. > > +- renesas,rxc-delay-ps: Internal RX clock delay. > > may be it make sense to add a generic delay property for MACs and PHYs? See Dan Murphys "RGMII Internal delay common property" patchset. That patchset is addressing the PHY side. Maybe we can build on that to address the MAC side? Andrew